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High Performance FSK/ASK Transceiver IC ADF7020-1
FEATURES
Low power, low IF transceiver Frequency bands 135 MHz to 650 MHz, direct output 80 MHz to 325 MHz, divide-by-2 mode Data rates supported 0.15 kbps to 200 kbps, FSK 0.15 kbps to 64 kbps, ASK 2.3 V to 3.6 V power supply Programmable output power -20 dBm to +13 dBm in 63 steps Receiver sensitivity -119 dBm at 1 kbps, FSK, 315 MHz -114 dBm at 9.6 kbps, FSK, 315 MHz -111.8 dBm at 9.6 kbps, ASK, 315 MHz Low power consumption 17.6 mA in receive mode 21 mA in transmit mode (10 dBm output) On-chip VCO and fractional-N PLL On-chip 7-bit ADC and temperature sensor Fully automatic frequency control loop (AFC) compensates for lower tolerance crystals Digital RSSI Integrated TRx switch Leakage current <1 A in power-down mode
APPLICATIONS
Low cost wireless data transfer Wireless medical applications Remote control/security systems Wireless metering Keyless entry Home automation Process and building control
FUNCTIONAL BLOCK DIAGRAM
RSET CREG(1:4) ADCIN MUXOUT
RLNA
POLARIZATION
LDO(1:4)
OFFSET CORRECTION
TEMP SENSOR
TEST MUX
LNA
RFIN RFINB IF FILTER
RSSI
MUX
7-BIT ADC
FSK/ASK DEMODULATOR
DATA SYNCHRONIZER
GAIN OFFSET CORRECTION AGC CONTROL
FSK MOD CONTROL GAUSSIAN FILTER - MODULATOR
CE DATA CLK
Tx/Rx CONTROL
DATA I/O
AFC CONTROL
INT/LOCK
RFOUT
DIVIDERS/ MUXING
DIV P
N/N+1 SLE
SERIAL PORT VCO CP PFD DIV R
RING OSC CLK DIV
SDATA SREAD SCLK
L1
L2
VCOIN
CPOUT
OSC1
OSC2
CLKOUT
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c) 2005 Analog Devices, Inc. All rights reserved.
05669-001
ADF7020-1 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 General Description ......................................................................... 3 Specifications..................................................................................... 4 Timing Characteristics ................................................................ 8 Absolute Maximum Ratings.......................................................... 10 ESD Caution................................................................................ 10 Pin Configuration and Function Descriptions........................... 11 Typical Performance Characteristics ........................................... 13 Frequency Synthesizer ................................................................... 15 Reference Input........................................................................... 15 Choosing Channels for Best System Performance................. 17 Transmitter ...................................................................................... 18 RF Output Stage.......................................................................... 18 Modulation Schemes.................................................................. 18 Receiver Section.............................................................................. 20 RF Front End............................................................................... 20 RSSI/AGC.................................................................................... 21 FSK Demodulators on the ADF7020-1 ................................... 21 FSK Correlator/Demodulator................................................... 21 Linear FSK Demodulator .......................................................... 23 AFC Section ................................................................................ 23 Automatic Sync Word Recognition ......................................... 24 Applications..................................................................................... 25 LNA/PA Matching...................................................................... 25 Transmit Protocol and Coding Considerations ..................... 26 Device Programming after Initial Power-Up ......................... 26 Interfacing to Microcontroller/DSP ........................................ 26 Serial Interface ................................................................................ 29 Readback Format........................................................................ 29 Register 0--N Register............................................................... 30 Register 1--Oscillator/Filter Register...................................... 31 Register 2--Transmit Modulation Register (ASK/OOK Mode) ..................................................................... 32 Register 2--Transmit Modulation Register (FSK Mode) ..... 33 Register 2--Transmit Modulation Register (GFSK/GOOK Mode)................................................................ 34 Register 3--Receiver Clock Register ....................................... 35 Register 4--Demodulator Set-up Register.............................. 36 Register 5--Sync Byte Register................................................. 37 Register 6--Correlator/Demodulator Register ...................... 38 Register 7--Readback Set-up Register .................................... 39 Register 8--Power-Down Test Register .................................. 40 Register 9--AGC Register......................................................... 41 Register 10--AGC 2 Register.................................................... 42 Register 11--AFC Register ....................................................... 42 Register 12--Test Register......................................................... 43 Register 13--Offset Removal and Signal Gain Register ....... 44 Outline Dimensions ....................................................................... 45 Ordering Guide .......................................................................... 45
REVISION HISTORY
12/05--Revision 0: Initial Version
Rev. 0 | Page 2 of 48
ADF7020-1 GENERAL DESCRIPTION
The ADF7020-1 is a low power, highly integrated FSK/GFSK/ ASK/OOK/GOOK transceiver designed for operation in the low UHF and VHF bands. The ADF7020-1 uses an external VCO inductor that allows users to set the operating frequency anywhere between 135 MHz and 650 MHz. Using the divideby-2 circuit allows users to operate the device as low as 80 MHz. The typical range of the VCO is about 10% of the operating frequency. A complete transceiver can be built using a small number of external discrete components, making the ADF70201 very suitable for price-sensitive and area-sensitive applications. The transmit section contains a VCO and low noise fractional-N PLL with output resolution of <1 ppm. This frequency agile PLL allows the ADF7020-1 to be used in frequency-hopping spread spectrum (FHSS) systems. The VCO operates at twice the fundamental frequency to reduce spurious emissions and frequency pulling problems. The transmitter output power is programmable in 63 steps from -20 dBm to +13 dBm. The transceiver RF frequency, channel spacing, and modulation are programmable using a simple 3wire interface. The device operates with a power supply range of 2.3 V to 3.6 V and can be powered down when not in use. A low IF architecture is used in the receiver (200 kHz), minimizing power consumption and the external component count and avoiding interference problems at low frequencies. The ADF7020-1 supports a wide variety of programmable features, including Rx linearity, sensitivity, and IF bandwidth, allowing the user to trade off receiver sensitivity and selectivity for current consumption, depending on the application. The receiver also features a patent-pending automatic frequency control (AFC) loop, allowing the PLL to compensate for frequency error in the incoming signal. An on-chip ADC provides readback of an integrated temperature sensor, an external analog input, the battery voltage, or the RSSI signal, which provides savings on an ADC in some applications. The temperature sensor is accurate to 10C over the full operating temperature range of -40C to +85C. This accuracy can be improved by doing a 1-point calibration at room temperature and storing the result in memory.
Rev. 0 | Page 3 of 48
ADF7020-1 SPECIFICATIONS
VDD = 2.3 V to 3.6 V, GND = 0 V, TA = TMIN to TMAX, unless otherwise noted. Typical specifications are at VDD = 3 V, TA = 25C. All measurements are performed using the EVAL-ADF7020-1-DBX and PN9 data sequence, unless otherwise noted. Table 1.
Parameter RF CHARACTERISTICS Frequency Ranges (Direct Output) Frequency Ranges (Divide-by-2 Mode) VCO Frequency Range Phase Frequency Detector Frequency TRANSMISSION PARAMETERS Data Rate FSK/GFSK OOK/ASK OOK/ASK Frequency Shift Keying GFSK/FSK Frequency Deviation 2, 3 Deviation Frequency Resolution Gaussian Filter BT Amplitude Shift Keying ASK Modulation Depth OOK-PA Off Feedthrough Transmit Power 4 Transmit Power Transmit Power Variation vs. Temp. Transmit Power Variation vs. VDD Programmable Step Size -20 dBm to +13 dBm Integer Boundary Reference Harmonics Second Harmonic Third Harmonic All Other Harmonics VCO Frequency Pulling, OOK Mode Optimum PA Load Impedance 5 Min 135 80 1.1 RF/256 1.2 20.96 Typ Max 650 325 Unit MHz MHz Ratio MHz FMAX/FMIN, using VCO bias settings in Table 5 PFD must be less than direct output frequency/31 Test Conditions See Table 5 for VCO bias settings at different frequencies
0.15 0.15 0.3 1 4.88 100 0.5
200 64 1 100 110 620
kbps kbps kbaud kHz kHz Hz
Using Manchester biphase-L encoding PFD = 3.625 MHz PFD = 20 MHz PFD = 3.625 MHz
30 -50 -20 -20 1 1 +13 +11
dB dBm dBm dBm dB dB
VDD = 3.0 V, TA = 25C, FRF > 200 MHz VDD = 3.0 V, TA = 25C, FRF < 200 MHz From -40C to +85C From 2.3 V to 3.6 V at 315 MHz, TA = 25C
0.3125 -55 -65 -27 -21 -35 30 79.4 + j64 109 + j64 40 + j47.5
dB dBc dBc dBc dBc dBc kHz rms
See Figure 13 for how output power varies with PA setting 50 kHz loop BW
Unfiltered conductive
DR = 9.6 kbps FRF = 140 MHz FRF = 320 MHz FRF = 590 MHz
Rev. 0 | Page 4 of 48
ADF7020-1
Parameter RECEIVER PARAMETERS FSK/GFSK Input Sensitivity Sensitivity at 1 kbps Sensitivity at 9.6 kbps OOK Input Sensitivity Sensitivity at 1 kbps Sensitivity at 9.6 kbps LNA and Mixer, Input IP37 Enhanced Linearity Mode Low Current Mode High Sensitivity Mode Rx Spurious Emissions 8 AFC Pull-In Range Response Time Accuracy CHANNEL FILTERING Adjacent Channel Rejection (Offset = 1 x IF Filter BW Setting) Second Adjacent Channel Rejection (Offset = 2 x IF Filter BW Setting) Third Adjacent Channel Rejection (Offset = 3 x IF Filter BW Setting) Image Channel Rejection CO-CHANNEL REJECTION Wideband Interference Rejection BLOCKING 1 MHz 5 MHz 10 MHz 10 MHz (High Linearity Mode) Saturation (Maximum Input Level) LNA Input Impedance Min Typ Max Unit Test Conditions At BER = 1E - 3, FRF = 315 MHz, LNA and PA matched separately 6 FDEV= 5 kHz, high sensitivity mode 7 FDEV = 10 kHz, high sensitivity mode At BER = 1E - 3, FRF = 315 MHz High sensitivity mode High sensitivity mode Pin = -20 dBm, 2 CW interferers, FRF = 315 MHz, F1 = FRF + 3 MHz, F2 = FRF + 6 MHz, maximum gain <1 GHz at antenna input >1 GHz at antenna input IF_BW = 200 kHz Modulation index = 0.875
-119.2 -114.2 -118.2 -111.8 6.8 -3.2 -35 -57 -47 50 48 1 27
dBm dBm dBm dBm dBm dBm dBm dBm dBm kHz Bits kHz dB
50
dB
IF filter BW settings = 100 kHz, 150 kHz, 200 kHz; desired signal 3 dB above the input sensitivity level; CW interferer power level increased until BER = 10-3; image channel excluded
55
dB
35 -2 70
dB dB dB
Image at FRF - 400 kHz Swept from 100 MHz to 2 GHz, measured as channel rejection Desired signal 3 dB above the input sensitivity level, CW interferer power level increased until BER = 10-2
60 68 65 72 12 237 - j193 101.4 - j161.6 49.3 - j104.6 -100 to -36 2 3 150
dB dB dB dB dBm dBm dB dB s
FSK mode, BER = 10-3 FRF = 130 MHz, RFIN to GND FRF = 310 MHz FRF = 610 MHz
RSSI Range at Input Linearity Absolute Accuracy Response Time
See the RSSI/AGC section
Rev. 0 | Page 5 of 48
ADF7020-1
Parameter PHASE-LOCKED LOOP VCO Gain Min Typ 40 35 16.5 Phase Noise (In-Band) Normalized In-Band Phase Noise Floor 9 Phase Noise (Out-of-Band) Residual FM PLL Settling -89 -198 -110 128 40 Max Unit MHz/V MHz/V MHz/V dBc/Hz dBc/Hz dBc/Hz Hz s 1 MHz offset From 200 Hz to 20 kHz, FRF = 315 MHz Measured for a 10 MHz frequency step to within 5 ppm accuracy, PFD = 20 MHz, LBW = 50 kHz Must ensure PFD maximum is not exceeded Refer to the crystal's data sheet 11.0592 MHz crystal, using 33 pF load capacitors Using 16 pF load capacitors See the Reference Input section Test Conditions 433 MHz, VCO adjust = 0, VCO_BIAS_SETTING = 2 315 MHz, VCO adjust = 0, VCO_BIAS_SETTING = 2 135 MHz, VCO adjust = 0, VCO_BIAS_SETTING = 1 PA = 0 dBm, VDD = 3.0 V, PFD = 10 MHz, FRF = 315 MHz, VCO_BIAS_SETTING = 2
REFERENCE INPUT Crystal Reference External Oscillator Load Capacitance Crystal Start-Up Time
3.625 3.625 33 2.1 1.0
24 24
MHz MHz pF ms ms CMOS levels LSB LSB s ms
Input Level ADC PARAMETERS INL DNL TIMING INFORMATION Chip Enabled to Regulator Ready Chip Enabled to RSSI Ready Tx-to-Rx Turnaround Time
1 1 10 3.0 150 s + (5 x TBIT)
From 2.3 V to 3.6 V, TA = 25C From 2.3 V to 3.6 V, TA = 25C CREG = 100 nF See Table 13 for more details Time to synchronized data out, includes AGC settling. See AGC Information and Timing section for more details.
LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINH/IINL Input Capacitance, CIN Control Clock Input LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL CLKOUT Rise/Fall CLKOUT Load TEMPERATURE RANGE--TA
0.7 x V DD 0.2 x V DD 1 10 50 DVDD - 0.4 0.4 5 10 +85
V V A pF MHz V V ns pF C IOH = 500 A IOL = 500 A
-40
Rev. 0 | Page 6 of 48
ADF7020-1
Parameter POWER SUPPLIES Voltage Supply VDD Transmit Current Consumption 433 MHz, 0 dBm/5 dBm/10 dBm Receive Current Consumption Low Current Mode High Sensitivity Mode Power-Down Mode Low Power Sleep Mode
1 2
Min
Typ
Max
Unit
Test Conditions
2.3
3.6
V
13/16/21 17.6 20.1 0.1 1
mA mA mA A
All VDD pins must be tied together FRF = 315 MHz, VDD = 3.0 V, PA is matched to 50 VCO_BIAS_SETTING = 2 VCO_BIAS_SETTING = 2 VCO_BIAS_SETTING = 2
Higher data rates are achievable, depending on local regulations. For definition of frequency deviation, see the Register 2--Transmit Modulation Register (FSK Mode) section. 3 For definition of GFSK frequency deviation, see the Register 2--Transmit Modulation Register (GFSK/GOOK Mode) section. 4 Measured as maximum unmodulated power. Output power varies with both supply and temperature. 5 For matching details, see the LNA/PA Matching section. 6 Sensitivity for combined matching network case is typically 2 dB less than separate matching networks. See Table 11 for sensitivity values at various data rates and frequencies. 7 See Table 6 for a description of different receiver modes. 8 Follow the matching and layout guidelines to achieve the relevant FCC/ETSI specifications. 9 This figure can be used to calculate the in-band phase noise for any operating frequency. Use the following equation to calculate the in-band phase noise performance as seen at the PA output: -198 + 10 log(fPFD) + 20 log N.
Rev. 0 | Page 7 of 48
ADF7020-1
TIMING CHARACTERISTICS
VDD = 3 V 10%, VGND = 0 V, TA = 25C, unless otherwise noted. Guaranteed by design, but not production tested. Table 2.
Parameter t1 t2 t3 t4 t5 t6 t8 t9 t10 Limit at TMIN to TMAX <10 <10 <25 <25 <10 <20 <25 <25 <10 Unit ns ns ns ns ns ns ns ns ns Test Conditions/Comments SDATA-to-SCLK set-up time SDATA-to-SCLK hold time SCLK high duration SCLK low duration SCLK-to-SLE set-up time SLE pulse width SCLK-to-SREAD data valid, readback SREAD hold time after SCLK, readback SCLK-to-SLE disable time, readback
t3
SCLK
t4
t1
t2
DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1)
SDATA
DB31 (MSB)
DB30
DB2
t6
SLE
t5
Figure 2. Serial Interface Timing Diagram
t1
SCLK
t2
SDATA REG7 DB0 (CONTROL BIT C1) SLE
t3
t10
X RV16 RV15 RV2 RV1
05669-003
SREAD
t8
t9
Figure 3. Readback Timing Diagram
Rev. 0 | Page 8 of 48
05669-002
ADF7020-1
1 x DATA RATE/32 1/DATA RATE
RxCLK
Figure 4. RxData/RxCLK Timing Diagram
1/DATA RATE TxCLK
TxDATA
DATA
NOTES 1. TxCLK ONLY AVAILABLE IN GFSK MODE.
Figure 5. TxData/TxCLK Timing Diagram
Rev. 0 | Page 9 of 48
05669-005
FETCH
SAMPLE
05669-004
RxDATA
DATA
ADF7020-1 ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. Table 3.
Parameter VDD to GND 1 Analog I/O Voltage to GND Digital I/O Voltage to GND Operating Temperature Range Industrial (B Version) Storage Temperature Range Maximum Junction Temperature MLF JA Thermal Impedance Reflow Soldering Peak Temperature Time at Peak Temperature
1
Rating -0.3 V to +5 V -0.3 V to AVDD + 0.3 V -0.3 V to DVDD + 0.3 V -40C to +85C -65C to +125C 150C 26C/W 260C 40 sec
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. This device is a high performance RF-integrated circuit with an ESD rating of <2 kV. It is ESD sensitive; proper precautions should be taken for handling and assembly.
GND = CPGND = RFGND = DGND = AGND = 0 V.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. 0 | Page 10 of 48
ADF7020-1 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
48 47 46 45 44 43 42 41 40 39 38 37 CVCO GND1 L1 GND L2 VDD CPOUT CREG3 VDD3 OSC1 OSC2 MUXOUT
VCOIN CREG1
1 2
PIN 1 INDICATOR
VDD1 3 RFOUT 4 RFGND 5 RFIN 6 RFINB 7 RLNA 8 VDD4 9 RSET 10 CREG4 11 GND4 12
ADF7020-1
TOP VIEW (Not to Scale)
36 35 34 33 32 31 30 29 28 27 26 25
CLKOUT DATA CLK DATA I/O INT/LOCK VDD2 CREG2 ADCIN GND2 SCLK SREAD SDATA SLE
MIX_I MIX_I MIX_Q MIX_Q FILT_I FILT_I GND4 FILT_Q FILT_Q GND4 TEST_A CE
13 14 15 16 17 18 19 20 21 22 23 24
Figure 6. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. 1 2 3 4 Mnemonic VCOIN CREG1 VDD1 RFOUT Description VCO Input Pin. The tuning voltage on this pin determines the output frequency of the voltage controlled oscillator (VCO). The higher the tuning voltage, the higher the output frequency. Regulator Voltage for PA Block. A 100 nF in parallel with a 5.1 pF capacitor should be placed between this pin and ground for regulator stability and noise rejection. Voltage Supply for PA Block. Decoupling capacitors of 0.1 F and 10 pF should be placed as close as possible to this pin. All VDD pins should be tied together. PA Output Pin. The modulated signal is available at this pin. Output power levels are from -20 dBm to +13 dBm. The output should be impedance matched to the desired load using suitable components. See the Transmitter section. Ground for Output Stage of Transmitter. All GND pins should be tied together. LNA Input for Receiver Section. Input matching is required between the antenna and the differential LNA input to ensure maximum power transfer. See the LNA/PA Matching section. Complementary LNA Input. See the LNA/PA Matching section. External Bias Resistor for LNA. Optimum resistor is 1.1 k with 5% tolerance. Voltage Supply for LNA/MIXER Block. This pin should be decoupled to ground with a 10 nF capacitor. External Resistor to Set Charge Pump Current and Some Internal Bias Currents. Use 3.6 k with 5% tolerance. Regulator Voltage for LNA/MIXER Block. A 100 nF capacitor should be placed between this pin and GND for regulator stability and noise rejection. Ground for LNA/MIXER Block. Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left unconnected. Ground for LNA/MIXER Block. Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left unconnected. Chip Enable. Bringing CE low puts the ADF7020-1 into complete power-down. Register values are lost when CE is low, and the part must be reprogrammed once CE is brought high. Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four latches. A latch is selected using the control bits. Serial Data Input. The serial data is loaded MSB first, with the 2 LSBs as the control bits. This pin is a high impedance CMOS input.
5 6 7 8 9 10 11 12 13 to 18 19, 22 20, 21, 23 24 25 26
RFGND RFIN RFINB RLNA VDD4 RSET CREG4 GND4 MIX/FILT GND4 FILT/TEST_A CE SLE SDATA
Rev. 0 | Page 11 of 48
05669-006
ADF7020-1
Pin No. 27 28 29 30 31 32 33 Mnemonic SREAD SCLK GND2 ADCIN CREG2 VDD2 INT/LOCK Description Serial Data Output. This pin is used to feed readback data from the ADF7020-1 to the microcontroller. The SCLK input is used to clock each readback bit (AFC, ADC readback) from the SREAD pin. Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the 24-bit shift register on the CLK rising edge. This pin is a digital CMOS input. Ground for Digital Section. Analog-to-Digital Converter Input. The internal 7-bit ADC can be accessed through this pin. Full scale is 0 to 1.9 V. Readback is made using the SREAD pin. Regulator Voltage for Digital Block. A 100 nF in parallel with a 5.1 pF capacitor should be placed between this pin and ground for regulator stability and noise rejection. Voltage Supply for Digital Block. A decoupling capacitor of 10 nF should be placed as close as possible to this pin. Bidirectional Pin. In output mode (interrupt mode), the ADF7020-1 asserts the INT/LOCK pin when it has found a match for the preamble sequence. In input mode (lock mode), the microcontroller can be used to lock the demodulator threshold when a valid preamble has been detected. Once the threshold is locked, NRZ data can be reliably received. In this mode, a demodulator lock can be asserted with minimum delay. Transmit Data Input/Received Data Output. This is a digital pin and normal CMOS levels apply. Transmit/Receive Clock Pin. In receive mode, the pin outputs the synchronized data clock. The positive clock edge is matched to the center of the received data. In GFSK transmit mode, the pin outputs an accurate clock to latch the data from the microcontroller into the transmit section at the exact required data rate. See the Gaussian Frequency Shift Keying (GFSK) section. A Divided-Down Version of the Crystal Reference with Output Driver. The digital clock output can be used to drive several other CMOS inputs such as a microcontroller clock. The output has a 50:50 mark-space ratio. Multiplexer Output Pin. This pin provides the Lock_Detect signal, which is used to determine if the PLL is locked to the correct frequency. Other signals include Regulator_Ready, which is an indicator of the status of the serial interface regulator. Oscillator Output Pin. The reference crystal should be connected between this pin and OSC1. A TCXO reference can be used by driving this pin with CMOS levels and disabling the crystal oscillator. Oscillator Input Pin. The reference crystal should be connected between this pin and OSC2. Voltage Supply for the Charge Pump and PLL Dividers. This pin should be decoupled to ground with a 0.01 F capacitor. Regulator Voltage for Charge Pump and PLL Dividers. A 100 nF in parallel with a 5.1 pF capacitor should be placed between this pin and ground for regulator stability and noise rejection. Charge Pump Output. This output generates current pulses that are integrated in the loop filter. The integrated current changes the control voltage on the input to the VCO. Voltage Supply for VCO Tank Circuit. This pin should be decoupled to ground with a 0.01 F capacitor. External VCO Inductor Pins. A chip inductor should be connected across these pins to set the VCO operating frequency. See the Voltage Controlled Oscillator (VCO) section for details on choosing the appropriate value. Grounds for VCO Block. VCO Noise Compensation Node. A 22 nF capacitor should be placed between this pin and CREG1 to reduce VCO noise.
34 35
DATA I/O DATA CLK
36 37
CLKOUT MUXOUT
38 39 40 41 42 43 44, 46 45, 47 48
OSC2 OSC1 VDD3 CREG3 CPOUT VDD L2, L1 GND, GND1 CVCO
Rev. 0 | Page 12 of 48
ADF7020-1 TYPICAL PERFORMANCE CHARACTERISTICS
CARRIER POWER -0.28dBm REF -70.00dBc/Hz 10.00 dB/
1
ATTEN 0.00dB
MKR1
10.0000kHz -87.80dBc/Hz
REF 10dBm PEAK 1 LOG 10dB/
ATTEN 20dB
MKR4 3.482GHz SWEEP 16.52ms (601pts)
3
4
REF LEVEL 10.00dBm
05669-007
1kHz
FREQUENCY OFFSET
10MHz
START 100MHz RES BW 3MHz
VBW 3MHz
STOP 10.000GHz SWEEP 16.52ms (601pts)
Figure 7. Phase Noise Response at 315 MHz, VDD = 3.0 V, ICP = 1.5 mA
Figure 10. Harmonic Response, RFOUT Matched to 50 , No Filter
REF 15dBm
REF 20dBm NORM LOG 10 dB/ ATTEN 30dB
ATTEN 30dB
Mkr1 1.834GHz -62.57dB
NORM 1R LOG 10dB/
FSK
MARKER 1.834000000GHz -62.57dB
LgAv
LgAv V1 V2 S3 FC AA (f): f>50k SWP GFSK
W1 S2 S3 FC AA (f): FTun Swp
05669-058
1
CENTER 415.000 0 MHz SPAN 400 kHz #RES BW 300 Hz VBW 300 Hz SWEEP 5.359 s (601pts)
START 800MHz #RES BW 30kHz
VBW 30kHz
STOP 5.000GHz SWEEP 5.627s (601pts)
Figure 8. Output Spectrum in FSK and GFSK Modulation
Figure 11. Harmonic Response, Murata Dielectric Filter
0 -5 -10 -15 200kHz FILTER BW
REF 20dBm NORM LOG 10 dB/
ATTEN 30dB
ATTENUATION LEVEL (dB)
-20 -25 -30 -35 -40 -45 -50 -55 -60 -65 -70 -400 -300 -200 -100 0 100 200 300 400 500 600 -350 -250 -150 -50 50 150 250 350 450 550 IF FREQ (kHz)
05669-009
OOK ASK
150kHz FILTER BW
LgAv V1 V2 S3 FC AA (f): f>50k SWP GOOK
100kHz FILTER BW
05669-011
05669-010
05669-059
CENTER 415.000 0 MHz SPAN 300 kHz #RES BW 360 Hz VBW 360 Hz SWEEP 2.791 s (601pts)
Figure 9. IF Filter Response
Figure 12. Output Spectrum in ASK, OOK, and GOOK Modes, DR = 10 kbps
Rev. 0 | Page 13 of 48
ADF7020-1
0
20 15 10 11A 9A
-1 -2 -3
+2.3V,+85C +2.3V,+25C +3.6V,+85C +2.3V,-40C +3.6V,-40C +3.6V,+25C +3.0V,-40C
PA OUTPUT POWER
5A 0 7A -5 -10
LOG (BER)
5
-4 -5 -6
-15
-7
-20
05669-013
-25 1 5 9 13 17 21 25 29 33 37 41 45 49 53 57 61 PA SETTING
INPUT POWER (dBm)
Figure 13. PA Output Power vs. Setting
Figure 16. Sensitivity vs. VDD and Temperature, RF = 315 MHz, DR = 1 kBPS, Correlator Demod
CARRIER POWER 10.75dBm REF -70.00dBc/Hz 10.00 dB/
ATTEN 6.00dB
MKR1
10.0000kHz -86.20dBc/Hz
0 -1 -2 -3 200.8k DATA RATE
BER
-4 -5 -6 -7 -8
1.002k DATA RATE
9.760k DATA RATE
-122 -121 -120 -119 -118 -117 -116 -115 -114 -113 -112 -111 -110 -109 -108 -107 -106 -105 -104 -103 -102 -101 -100 -99 -98 -97 -96 -95 -94 -93 -92 -91 -90
RF I/P LEVEL (dBm) LINEAR AFC OFF CORRELATION AFC ON CORRELATION AFC OFF LINEAR AFC ON FREQUENCY ERROR (kHz)
05669-018
1kHz
FREQUENCY OFFSET
10MHz
05669-057
Figure 14. Wideband Interference Rejection. Wanted Signal (880 MHz) at 3 dB above Sensitivity Point Interferer = FM Jammer (9.76 kbps, 10k Deviation)
Figure 17. BER vs. Data-Rate (Combined Matching Network) Separate LNA and PA Matching Paths Typically Improve Performance by 2 dB
-60
20
-65
0 -20 ACTUAL INPUT LEVEL
RF I/P LEVEL (dBm)
-70 -75
RSSI LEVEL (dB)
-80 -85 -90 -95 -100 -105 -110
-110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110
-40 RSSI READBACK LEVEL -60 -80 -100 -120 -120
-100
-80
-60 -40 RF I/P (dB)
-20
0
20
05669-015
Figure 15. Digital RSSI Readback Linearity
Figure 18. Sensitivity vs. Frequency Error with AFC On/Off
Rev. 0 | Page 14 of 48
05669-017
05669-016
-8 -127 -126 -125 -124 -123 -122 -121 -120 -119 -118 -117 -116 -115
ADF7020-1 FREQUENCY SYNTHESIZER
REFERENCE INPUT
The on-board crystal oscillator circuitry (see Figure 19) can use an inexpensive quartz crystal as the PLL reference. The oscillator circuit is enabled by setting R1_DB12 high. It is enabled by default on power-up and is disabled by bringing CE low. Errors in the crystal can be corrected using the automatic frequency control (see the AFC Section) feature or by adjusting the fractional-N value (see the N Counter section). A single-ended reference (TCXO, CXO) can also be used. The CMOS levels should be applied to OSC2 with R1_DB12 set low.
R Counter
The 3-bit R counter divides the reference input frequency by an integer from 1 to 7. The divided-down signal is presented as the reference clock to the phase frequency detector (PFD). The divide ratio is set in Register 1. Maximizing the PFD frequency reduces the N value. This reduces the noise multiplied at a rate of 20 log(N) to the output, as well as reducing occurrences of spurious components. The R Register defaults to R = 1 on power-up: PFD [Hz] = XTAL/R
MUXOUT and Lock Detect
OSC1 CP2 OSC2 CP1
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The MUXOUT pin allows the user to access various digital points in the ADF7020-1. The state of MUXOUT is controlled by Bits R0_DB (29:31).
Figure 19. Oscillator Circuit on the ADF7020-1
Regulator Ready
Regulator ready is the default setting on MUXOUT after the transceiver has been powered up. The power-up time of the regulator is typically 50 s. Because the serial interface is powered from the regulator, the regulator must be at its nominal voltage before the ADF7020-1 can be programmed. The status of the regulator can be monitored at MUXOUT. When the regulator ready signal on MUXOUT is high, programming of the ADF7020-1 can begin.
DVDD
Two parallel resonant capacitors are required for oscillation at the correct frequency; their values are dependent on the crystal specification. They should be chosen so that the series value of capacitance added to the PCB track capacitance adds up to the load capacitance of the crystal, usually 20 pF. Track capacitance values vary from 2 pF to 5 pF, depending on board layout. Where possible, choose capacitors that have a very low temperature coefficient to ensure stable frequency operation over all conditions.
CLKOUT Divider and Buffer
The CLKOUT circuit takes the reference clock signal from the oscillator section (see Figure 19) and supplies a divided-down 50:50 mark-space signal to the CLKOUT pin. An even divide from 2 to 30 is available. This divide number is set in R1_DB (8:11). On power-up, the CLKOUT defaults to the divide-by-8 block.
DVDD CLKOUT ENABLE BIT
05669-021
REGULATOR READY DIGITAL LOCK DETECT ANALOG LOCK DETECT R COUNTER OUTPUT N COUNTER OUTPUT PLL TEST MODES - TEST MODES MUX CONTROL MUXOUT
DGND
OSC1 DIVIDER 1 TO 15 /2
Figure 21. MUXOUT Circuit
CLKOUT
05669-020
Digital Lock Detect
Digital lock detect is active high. The lock detect circuit is located at the PFD. When the phase error on five consecutive cycles is less than 15 ns, lock detect is set high. Lock detect remains high until 25 ns phase error is detected at the PFD. Because no external components are needed for digital lock detect, it is more widely used than analog lock detect.
Figure 20. CLKOUT Stage
To disable CLKOUT, set the divide number to 0. The output buffer can drive up to a 20 pF load with a 10% rise time at 4.8 MHz. Faster edges can result in some spurious feedthrough to the output. A small series resistor (50 ) can be used to slow the clock edges to reduce these spurs at FCLK.
Rev. 0 | Page 15 of 48
ADF7020-1
Analog Lock Detect
This N-channel, open-drain lock detect should be operated with an external pull-up resistor of 10 k nominal. When a lock has been detected, this output is high with narrow low-going pulses. For GFSK, it is recommended that an LBW of 2.0 to 2.5 times the data rate be used to ensure that sufficient samples are taken of the input data while filtering system noise. The free design tool ADIsimPLL can be used to design loop filters for the ADF7020-1.
Voltage Regulators
The ADF7020-1 contains four regulators to supply stable voltages to the part. The nominal regulator voltage is 2.3 V. Each regulator should have a 100 nF capacitor connected between CREG and GND. When CE is high, the regulators and other associated circuitry are powered on, drawing a total supply current of 2 mA. Bringing the chip-enable pin low disables the regulators, reduces the supply current to less than 1 A, and erases all values held in the registers. The serial interface operates from a regulator supply; therefore, to write to the part, the user must have CE high and the regulator voltage must be stabilized. Regulator status (CREG4) can be monitored using the regulator ready signal from muxout.
N Counter
The feedback divider in the ADF7020-1 PLL consists of an 8-bit integer counter and a 15-bit - fractional-N divider. The integer counter is the standard pulse-swallow type common in PLLs. This sets the minimum integer divide value to 31. The fractional divide value gives very fine resolution at the output, where the output frequency of the PLL is calculated as
FOUT =
Fractional - N XTAL x (Integer - N + ) 215 R
REFERENCE IN 4\R PFD/ CHARGE PUMP VCO
Loop Filter
The loop filter integrates the current pulses from the charge pump to form a voltage that tunes the output of the VCO to the desired frequency. It also attenuates spurious levels generated by the PLL. A typical loop-filter design is shown in Figure 22.
4\N
THIRD-ORDER - MODULATOR
05669-023
FRACTIONAL-N
CHARGE PUMP OUT
INTEGER-N
Figure 23. Fractional-N PLL
VCO
Figure 22. Typical Loop-Filter Configuration
The combination of the integer-N (maximum = 255) and the fractional-N (maximum = 16,383/16,384) give a maximum N divider of 255 + 1. Therefore, the minimum usable PFD is PFDMIN [Hz] = Maximum Required Output Frequency/(255 + 1) For example, when operating at 620 MHz, PFDMIN equals 2.42 MHz.
In FSK, the loop should be designed so that the loop bandwidth (LBW) is approximately 5 times the data rate. Widening the LBW excessively reduces the time spent jumping between frequencies, but can cause insufficient spurious attenuation. For ASK systems, a wider LBW is recommended. The sudden large transition between two power levels might result in VCO pulling and can cause a wider output spectrum than is desired. By widening the LBW to more than 10 times the data rate, the amount of VCO pulling is reduced, because the loop settles quickly back to the correct frequency. The wider LBW might restrict the output power and data rate of ASK-based systems more than it would that of FSK-based systems. Narrow-loop bandwidths can result in the loop taking long periods of time to attain lock. Careful design of the loop filter is critical to obtaining accurate FSK/GFSK modulation.
05669-022
Voltage Controlled Oscillator (VCO)
The ADF7020-1 features an on-chip VCO with external tank inductor, which is used to set the frequency range. The center frequency of the VCO is set by the internal varactor capacitance and the combined inductance of the external chip inductor, bond wire, and PCB track. A plot of VCO operating range vs. total external inductance (chip inductor + PCB track) is shown in Figure 24. The inductance for a PCB track using FR4 material is approximately 0.57 nH/mm. This should be subtracted from the total value to determine the correct chip inductor value. An additional frequency divide-by-2 block is included to allow operation from 80 MHz to 325 MHz. To enable the divide-by-2 block, set R1_DB13 to 1.
Rev. 0 | Page 16 of 48
ADF7020-1
The VCO can be recentered, depending on the required frequency of operation, by programming the VCO adjust bits R1_DB (20:21). The VCO is enabled as part of the PLL by the PLL-enable bit, R0_DB28. The VCO needs an external 22 nF between the VCO and the regulator to reduce internal noise.
750 700 650
CHOOSING CHANNELS FOR BEST SYSTEM PERFORMANCE
The fractional-N PLL allows the selection of any channel within 80 MHz to 650 MHz to a resolution of <300 Hz. This also facilitates frequency-hopping systems. Careful selection of the RF transmit channels must be made to achieve best spurious performance. The architecture of fractional-N results in some level of the nearest integer channel moving through the loop to the RF output. These beat-note spurs are not attenuated by the loop if the desired RF channel and the nearest integer channel are separated by a frequency of less than the LBW. The occurrence of beat-note spurs is rare, because the integer frequencies are at multiples of the reference, which is typically >10 MHz.
FREQUENCY (MHz)
600 550 500 450 400 350 300 250 200 0 5
FMAX (MHz)
10
15
20
25
30
TOTAL EXTERNAL INDUCTANCE (nH)
Figure 24. External Inductance vs. Frequency
VCO Bias Current
VCO bias current can be adjusted using Bits R1_DB19 to R1_DB16. To minimize current consumption, the bias current setting should be as indicated in Table 5.
Table 5. Recommended VCO Bias Currents
Direct Frequency Output (f) f < 200 MHz 200 MHz < f < 450 MHz f > 450 MHz VCO Bias R1_DB(19:16) 0001 0010 0011
VCO BIAS R1_DB (16:19) /2
TO N DIVIDER VCO /2 MUX TO PA
LOOP FILTER
220F CVCO PIN
05669-025
VCO SELECT BIT
Figure 25. Voltage Controlled Oscillator (VCO)
05669-024
FMIN (MHz)
The amplitude of beat-note spurs can be significantly reduced by using the frequency doubler to avoid very small or very large values in the fractional register. By having a channel 1 MHz away from an integer frequency, a 100 kHz loop filter can reduce the level to <-45 dBc.
Rev. 0 | Page 17 of 48
ADF7020-1 TRANSMITTER
RF OUTPUT STAGE
The PA of the ADF7020-1 is based on a single-ended, controlled current, open-drain amplifier that has been designed to deliver up to 13 dBm into a 50 load at a maximum frequency of 650 MHz. The PA output current and, consequently, the output power are programmable over a wide range. The PA configurations in FSK/GFSK and ASK/OOK modulation modes are shown in Figure 26 and Figure 27, respectively. In FSK/GFSK modulation mode, the output power is independent of the state of the DATA_IO pin. In ASK/OOK modulation mode, it is dependent on the state of the DATA_IO pin and Bit R2_DB29, which selects the polarity of the TxData input. For each transmission mode, the output power can be adjusted as follows:
* *
The PA is equipped with overvoltage protection, which makes it robust in severely mismatched conditions. Depending on the application, users can design a matching network for the PA to exhibit optimum efficiency at the desired radiated output power level for a wide range of different antennas, such as loop or monopole antennas. See the LNA/PA Matching section for details.
PA Bias Currents
Control Bits R2_DB (30:31) facilitate an adjustment of the PA bias current to further extend the output power control range, if necessary. If this feature is not required, the default value of 9 A is recommended. The output stage is powered down by resetting Bit R2_DB4. To reduce the level of undesired spurious emissions, the PA can be muted during the PLL lock phase by toggling this bit.
FSK/GFSK: The output power is set using bits R2_DB (9:14). ASK: The output power for the inactive state of the TxData input is set by Bits R2_DB (15:20). The output power for the active state of the TxData input is set by Bits R2_DB (9:14). OOK: The output power for the active state of the TxData input is set by Bits R2_DB (9:14). The PA is muted when the TxData input is inactive.
R2_DB(30:31) 2 6
MODULATION SCHEMES
Frequency Shift Keying (FSK)
Frequency shift keying is implemented by setting the N value for the center frequency and then toggling this with the TxData line. The deviation from the center frequency is set using Bits R2_DB (15:23). The deviation from the center frequency in hertz is
FSK DEVIATION [Hz] = PFD x Modulation Number 214
*
where Modulation Number is a number from 1 to 511 (R2_DB (15:23)).
R2_DB(9:14)
IDAC
Select FSK using Bits R2_DB (6:8).
RFOUT R2_DB4 + R2_DB5 DIGITAL LOCK DETECT FROM VCO
05669-026
RFGND
4R
PFD/ CHARGE PUMP
PA STAGE VCO
Figure 26. PA Configuration in FSK/GFSK Mode
DATA I/O R2_DB29 ASK/OOK MODE
FSK DEVIATION FREQUENCY /N -FDEV
R2_DB(30:31) 6 IDAC 6 6 RFOUT + 0 R2_DB4 R2_DB5 DIGITAL LOCK DETECT FROM VCO R2_DB(9:14) R2_DB(15:23)
TxDATA FRACTIONAL-N INTEGER-N
Figure 28. FSK Implementation
Figure 27. PA Configuration in ASK/OOK Mode
Rev. 0 | Page 18 of 48
05669-027
RFGND
05669-028
+FDEV
THIRD-ORDER - MODULATOR
ADF7020-1
Gaussian Frequency Shift Keying (GFSK)
Gaussian frequency shift keying reduces the bandwidth occupied by the transmitted spectrum by digitally prefiltering the TxData. A TxCLK output line is provided from the ADF7020-1 for synchronization of TxData from the microcontroller. The TxCLK line can be connected to the clock input of a shift register that clocks data to the transmitter at the exact data rate.
Amplitude Shift Keying (ASK)
Amplitude shift keying is implemented by switching the output stage between two discrete power levels. This is accomplished by toggling the DAC, which controls the output level between two 6-bit values set up in Register 2. A 0 TxData bit sends Bits R2_DB (15:20) to the DAC. A high TxData bit sends Bits R2_DB (9:14) to the DAC. A maximum modulation depth of 30 dB is possible.
On-Off Keying (OOK)
On-off keying is implemented by switching the output stage to a certain power level for a high TxData bit and switching the output stage off for a low TxData bit. For OOK, the transmitted power for a high input is programmed using Bits R2_DB (9:14).
Setting Up the ADF7020-1 for GFSK
To set up the frequency deviation, set the PFD and the modulator control bits according to the following equation:
GFSK DEVIATION [Hz] =
PFD x 2 m 212
Gaussian On-Off Keying (GOOK)
Gaussian on-off keying represents a prefiltered form of OOK modulation. The usually sharp symbol transitions are replaced with smooth Gaussian filtered transitions, the result being a reduction in frequency pulling of the VCO. Frequency pulling of the VCO in OOK mode can lead to a wider than desired BW, especially if it is not possible to increase the loop-filter BW > 300 kHz. The GOOK sampling clock samples data at the data rate. (See the Setting Up the ADF7020-1 for GFSK section.)
where m is GFSK_MOD_CONTROL set using R2_DB (24:26). To set up the GFSK data rate, set the PFD and the modulator control bits according to the following equation:
DR [bps] = PFD DIVIDER _ FACTOR x INDEX _ COUNTER
where DIVIDER_FACTOR and INDEX_COUNTER are programmed in Bits R2_DB (15:21) and R2_DB (27:28), respectively. For further information, see the Using GFSK on the ADF7010 section in the EVAL-ADF7010EB1 data sheet.
Rev. 0 | Page 19 of 48
ADF7020-1 RECEIVER SECTION
RF FRONT END
The ADF7020-1 is based on a fully integrated, low IF receiver architecture. The low IF architecture facilitates a very low external component count and does not suffer from power-lineinduced interference problems. Figure 29 shows the structure of the receiver front end. The many programming options allow users to trade off sensitivity, linearity, and current consumption for each other in the most suitable way for their applications. To achieve a high level of resilience against spurious reception, the LNA features a differential input. Switch SW2 shorts the LNA input when transmit mode is selected (R0_DB27 = 0). This feature facilitates the design of a combined LNA/PA matching network, avoiding the need for an external Rx/Tx switch. See the LNA/PA Matching section for details on the design of the matching network.
I (TO FILTER) RFIN Tx/Rx SELECT [R0_DB27] RFINB LNA MODE [R6_DB15] LNA CURRENT [R6_DB(16:17)] LNA GAIN [R9_DB(20:21)] LNA/MIXER ENABLE [R8_DB6]
The LNA has two basic operating modes: high gain/low noise mode and low gain/low power mode. To switch between these two modes, use the LNA_mode bit, R6_DB15. The mixer is also configurable between a low current and an enhanced linearity mode using the mixer_linearity bit, R6_DB18. Based on the specific sensitivity and linearity requirements of the application, it is recommended to adjust control bits LNA_mode (R6_DB15) and mixer_linearity (R6_DB18) as outlined in Table 6. The gain of the LNA is configured by the LNA_gain field, R9_DB (20:21), and can be set by either the user or the automatic gain control (AGC) logic.
IF Filter Settings/Calibration
Out-of-band interference is rejected by means of a fourth-order Butterworth polyphase IF filter centered around a frequency of 200 kHz. The bandwidth of the IF filter can be programmed between 100 kHz and 200 kHz by means of Control Bits R1_DB (22:23); it should be chosen as a compromise between interference rejection, attenuation of the desired signal, and the AFC pull-in range. To compensate for manufacturing tolerances, the IF filter should be calibrated once after power-up. The IF filter calibration logic requires that the IF filter divider in Bits R6_DB (20:28) be set dependent on the crystal frequency. Once initiated by setting Bit R6_DB19, the calibration is performed automatically without any user intervention. The calibration time is 200 s, during which the ADF7020-1 should not be accessed. It is important not to initiate the calibration cycle before the crystal oscillator has fully settled. If the AGC loop is disabled, the gain of IF filter can be set to three levels using the filter_gain field, R9_DB (22:23). The filter gain is adjusted automatically, if the AGC loop is enabled.
SW2
LNA
LO
Q (TO FILTER) MIXER LINEARITY [R6_DB18]
Figure 29. ADF7020-1 RF Front End
The LNA is followed by a quadrature down conversion mixer, which converts the RF signal to the IF frequency of 200 kHz. It is important to consider that the output frequency of the synthesizer must be programmed to a value 200 kHz below the center frequency of the received channel.
Table 6. LNA/Mixer Modes
LNA Mode (R6_DB15) 0 1 1 1 1 0 LNA Gain Value R9_DB (21:20) 30 10 3 3 10 30 Mixer Linearity (R6_DB18) 0 0 0 1 1 1 Sensitivity (DR = 9.6 kbps, fDEV = 10 kHz) -112.5 -105.8 -92.2 -102.5 -99 -105 Rx Current Consumption (mA) 20.1 19.0 17.6 17.6 19.0 20.1 Input IP3 (dBm) -35 -15.9 -3.2 +6.8 -8.25 -28.8
Receiver Mode High Sensitivity Mode (default) RxMode2 Low Current Mode Enhanced Linearity Mode RxMode5 RxMode6
Rev. 0 | Page 20 of 48
05669-029
ADF7020-1
RSSI/AGC
The RSSI is implemented as a successive compression log amp following the base-band channel filtering. The log amp achieves 3 dB log linearity. It also doubles as a limiter to convert the signal-to-digital levels for the FSK demodulator. The RSSI itself is used for amplitude shift keying (ASK) demodulation. In ASK mode, extra digital filtering is performed on the RSSI value. Offset correction is achieved using a switched capacitor integrator in feedback around the log amp. This uses the BB offset clock divide. The RSSI level is converted for user readback and digitally controlled AGC by an 80-level (7-bit) flash ADC. This level can be converted to input power in dBm.
OFFSET CORRECTION FSK DEMOD
AGC _ Wait _ Time =
AGC _ DELAY x SEQ _ CLK _ DIVIDE XTAL
AGC Settling = AGC_Wait_Time x Number of Gain Changes Thus, in the worst case, if the AGC loop has to go through all five gain changes, AGC delay = 10, and SEQ_CLK = 200 kHz, then AGC settling = 10 x 5 s x 5 = 250 s. Minimum AGC_Wait_Time must be at least 25 s.
RSSI Formula (Converting to dBm)
Input_Power [dBm] = -120 dBm + (Readback_Code + Gain_Mode_Correction) x 0.5 where: Readback_Code is given by Bits RV7 to RV1 in the readback register (see Readback Format section). Gain_Mode_Correction is given by the values in Table 7. LNA gain and filter gain (LG2/LG1, FG2/FG1) are also obtained from the readback register.
1
A
A
A
LATCH
IFWR
IFWR
IFWR
IFWR
CLK ADC
RSSI ASK DEMOD
05669-030
R
Table 7. Gain Mode Correction
LNA Gain (LG2, LG1) H (1, 1) M (1, 0) M (1, 0) M (1, 0) L (0, 1) EL (0, 0) Filter Gain (FG2, FG1) H (1, 0) H (1, 0) M (0, 1) L (0, 0) L (0, 0) L (0, 0) Gain Mode Correction 0 24 45 63 90 105
Figure 30. RSSI Block Diagram
RSSI Thresholds
When the RSSI is above AGC_HIGH_THRESHOLD, the gain is reduced. When the RSSI is below AGC_LOW_THRESHOLD, the gain is increased. A delay (AGC_DELAY) is programmed to allow for settling of the loop. The user programs the two threshold values (recommended defaults, 30 and 70) and the delay (default, 10). The default AGC set-up values should be adequate for most applications. The threshold values must be more than 30 settings apart for the AGC to operate correctly.
An additional factor should be introduced to account for losses in the front-end matching network/antenna.
FSK DEMODULATORS ON THE ADF7020-1
The two FSK demodulators on the ADF7020-1 are
* *
Offset Correction Clock
In Register 3, the user should set the BB offset clock divide bits R3_DB (4:5) to give an offset clock between 1 MHz and 2 MHz, where: BBOS_CLK (Hz) = XTAL/(BBOS_CLK_DIVIDE) BBOS_CLK_DIVIDE can be set to 4, 8, or 16.
FSK correlator/demodulator Linear demodulator
Select these using the demodulator select bits, R4_DB (4:5).
FSK CORRELATOR/DEMODULATOR
The quadrature outputs of the IF filter are first limited and then fed to a pair of digital frequency correlators that perform bandpass filtering of the binary FSK frequencies at (IF + FDEV) and (IF - FDEV). Data is recovered by comparing the output levels from each of the two correlators. The performance of this frequency discriminator approximates that of a matched filter detector, which is known to provide optimum detection in the presence of AWGN.
AGC Information and Timing
AGC is selected by default, and operates by selecting the appropriate LNA and filter gain settings for the measured RSSI level. It is possible to disable AGC by writing to Register 9 if you want to enter one of the modes listed in Table 6, for example. The time for the AGC circuit to settle and hence the time it takes to take an accurate RSSI measurement is typically 150 s, although this depends on how many gain settings the AGC circuit has to cycle through. After each gain change, the AGC loop waits for a programmed time to allow transients to settle. This wait time can be adjusted to speed up this settling by adjusting the appropriate parameters.
Rev. 0 | Page 21 of 48
ADF7020-1
FREQUENCY CORRELATOR SLICER
LIMITERS Q IF - FDEV IF + FDEV
POST DEMOD FILTER
I
DATA SYNCHRONIZER
IF
Rx DATA
Rx CLK
where: DEMOD_CLK is as defined in the Register 3--Receiver Clock Register section, Note 2. K = round(200e3/FSK deviation) To optimize the coefficients of the FSK correlator, two additional bits, R6_DB14 and R6_DB29, must be assigned. The value of these bits depends on whether K (as defined above) is odd or even. These bits are assigned according to the conditions listed in Table 8 and Table 9.
Table 8. When K Is Even
K Even Even K/2 Even Odd R6_DB14 0 0 R6_DB29 0 1
DB(4:13) DB(14)
DB(8:15)
Figure 31. FSK Correlator/Demodulator Block Diagram
Postdemodulator Filter
A second-order digital low-pass filter removes excess noise from the demodulated bit stream at the output of the discriminator. The bandwidth of this postdemodulator filter is programmable and must be optimized for the user's data rate. If the bandwidth is set too narrow, performance is degraded due to intersymbol interference (ISI). If the bandwidth is set too wide, excess noise degrades the receiver's performance. Typically, the 3 dB bandwidth of this filter is set at approximately 0.75 times the user's data rate, using Bits R4_DB (6:15).
05669-031
0
Table 9. When K Is Odd
K Odd Odd (K + 1)/2 Even Odd R6_DB14 1 1 R6_DB29 0 1
Bit Slicer
The received data is recovered by the threshold detecting the output of the postdemodulator low-pass filter. In the correlator/ demodulator, the binary output signal levels of the frequency discriminator are always centered on zero. Therefore, the slicer threshold level can be fixed at zero, and the demodulator performance is independent of the run-length constraints of the transmit data bit stream. This results in robust data recovery, which does not suffer from the classic baseline wander problems that exist in the more traditional FSK demodulators. Frequency errors are removed by an internal AFC loop that measures the average IF frequency at the limiter output and applies a frequency correction value to the fractional-N synthesizer. This loop should be activated when the frequency errors are greater than approximately 40% of the transmit frequency deviation (see the AFC Section).
Postdemodulator Bandwidth Register Settings
The 3 dB bandwidth of the postdemodulator filter is controlled by Bits R4_ DB (6:15) and is given by
Post _ Demod _ BW _ Setting = 2 10 x 2 x FCUTOFF DEMOD _ CLK
where FCUTOFF is the target 3 dB bandwidth in hertz of the postdemodulator filter. This should typically be set to 0.75 times the data rate (DR). Some sample settings for the FSK correlator/demodulator are DEMOD_CLK = 5 MHz DR = 9.6 kbps FDEV = 20 kHz Therefore FCUTOFF = 0.75 x 9.6 x 103 Hz Post_Demod_BW = 211 7.2 x 103 Hz/(5 MHz) Post_Demod_BW = Round(9.26) = 9 and K = Round(200 kHz)/20 kHz) = 10 Discriminator_BW = (5 MHz x 10)/(800 x 103) = 62.5 = 63 (rounded to nearest integer)
Table 10. Register Settings
Setting Name Post_Demod_BW Discriminator_BW Dot Product Rx Data Invert Register Address R4_DB (6:15) R6_DB (4:13) R6_DB14 R6_DB29 Value 0x09 0x3F 0 1
Data Synchronizer
An oversampled digital PLL is used to resynchronize the received bit stream to a local clock. The oversampled clock rate of the PLL (CDR_CLK) must be set at 32 times the data rate. See the notes for the Register 3--Receiver Clock Register section for a definition of how to program the various on-chip clocks. The clock recovery PLL can accommodate frequency errors of up to 2%.
FSK Correlator Register Settings
To enable the FSK correlator/demodulator, Bits R4_DB (5:4) should be set to [01]. To achieve best performance, the bandwidth of the FSK correlator must be optimized for the specific deviation frequency that is used by the FSK transmitter. The discriminator BW is controlled in Register 6 by R6_DB (4:13) and is defined as
Discriminator _ BW = (DEMOD _ CLK x K ) /(800 x 10 3 )
Rev. 0 | Page 22 of 48
ADF7020-1
LINEAR FSK DEMODULATOR
Figure 32 shows a block diagram of the linear FSK demodulator.
MUX 1 ADC RSSI OUTPUT LEVEL IF 7 SLICER
Post_Demod_BW_Setting =
210 x 2 x FCUTOFF DEMOD_CLK
where FCUTOFF is the target 3 dB bandwidth in hertz of the postdemodulator filter. It is also recommended to use Manchester encoding in ASK/OOK mode to ensure the data run length limit (RLL) is 2 bits. If a longer RLL, up to a maximum of 4 bits, is required, users should disable the extra-low gain setting by writing 0x3C00C to the test mode register.
Q FREQUENCY LINEAR DISCRIMINATOR
ENVELOPE DETECTOR
LIMITER
AVERAGING FILTER
I
Rx DATA
05669-032
FREQUENCY READBACK AND AFC LOOP
DB(6:15)
AFC SECTION
The ADF7020-1 supports a real-time AFC loop, which is used to remove frequency errors that can arise due to mismatches between the transmit and receive crystals. The AFC loop uses the frequency discriminator block as described in the Linear FSK Demodulator section (see Figure 32). The discriminator output is filtered and averaged to remove the FSK frequency modulation using a combined averaging filter and envelope detector. In FSK mode, the output of the envelope detector provides an estimate of the average IF frequency. Two methods of AFC, external and internal, are supported on the ADF7020-1 (in FSK mode only).
Figure 32. Block Diagram of Frequency Measurement System and ASK/OOK/Linear FSK Demodulator
This method of frequency demodulation is useful when very short preamble length is required and the system protocol cannot support the overhead of the settling time of the internal feedback AFC loop settling. A digital frequency discriminator provides an output signal that is linearly proportional to the frequency of the limiter outputs. The discriminator output is then filtered and averaged using a combined averaging filter and envelope detector. The demodulated FSK data is recovered by comparing the filter output with its average value, as shown in Figure 32. In this mode, the slicer output shown in Figure 32 is routed to the data synchronizer PLL for clock synchronization. To enable the linear FSK demodulator, set Bits R4_DB (4:5) to [00]. The 3 dB bandwidth of the postdemodulation filter is set in the same way as the FSK correlator/demodulator, which is set in R4_DB (6:15) and is defined as
Post _ Demod _ BW _ Setting = 210 x 2 x FCUTOFF DEMOD _ CLK
External AFC
The user reads back the frequency information through the ADF7020-1 serial port and applies a frequency correction value to the fractional-N synthesizer's N divider. The frequency information is obtained by reading the 16-bit signed AFC_readback, as described in the Readback Format section, and applying the following formula: FREQ_RB [Hz] = (AFC_READBACK x DEMOD_CLK)/215 Note that while the AFC_READBACK value is a signed number, under normal operating conditions it is positive. In the absence of frequency errors, the FREQ_RB value is equal to the IF frequency of 200 kHz.
where: FCUTOFF is the target 3 dB bandwidth in hertz of the postdemodulator filter. DEMOD_CLK is as defined in the Register 3--Receiver Clock Register section, Note 2.
Internal AFC
The ADF7020-1 supports a real-time internal automatic frequency control loop. In this mode, an internal control loop automatically monitors the frequency error and adjusts the synthesizer N divider using an internal PI control loop. The internal AFC control loop parameters are controlled in Register 11. The internal AFC loop is activated by setting R11_DB20 to 1. A scaling coefficient must also be entered, based on the crystal frequency in use. This is set up in R11_DB (4:19) and should be calculated using AFC_Scaling_Coefficient = (500 x 224)/XTAL Therefore, using a 10 MHz XTAL yields an AFC scaling coefficient of 839.
Rev. 0 | Page 23 of 48
ASK/OOK Operation
ASK/OOK demodulation is activated by setting Bits R4_DB (4:5) to [10]. ASK/OOK demodulation is performed by digitally filtering the RSSI output, and then comparing the filter output with its average value in a similar manner to FSK demodulation. The bandwidth of the digital filter must be optimized to remove any excess noise without causing ISI in the received ASK/OOK signal. The 3 dB bandwidth of this filter is typically set at approximately 0.75 times the user data rate and is assigned by R4 _DB (6:15) as
ADF7020-1
AFC Performance
The improved sensitivity performance of the Rx when AFC is enabled and in the presence of frequency errors is shown in Figure 18. The maximum AFC pull-in range is 50 kHz, which corresponds to 58 ppm at 868 MHz. This is the total error tolerance allowed in the link. For example, in a point-to-point system, AFC can compensate for two 29 ppm crystals or one 50 ppm crystal and one 8 ppm TCXO. AFC settling typically takes 48 bits to settle within 1 kHz. This can be improved by increasing the postdemodulator bandwidth in Register 4 at the expense of Rx sensitivity. When AFC errors have been removed using either the internal or external AFC, further improvement in the receiver's sensitivity can be obtained by reducing the IF filter bandwidth using Bits R1_DB (22:23). preprogrammed word is compared to the received bit stream, and the external pin INT/LOCK is asserted by the ADF7020-1 when a valid match is identified. This feature can be used to alert the microprocessor that a valid channel has been detected. It relaxes the computational requirements of the microprocessor and reduces the overall power consumption. The INT/LOCK is automatically deasserted again after nine data clock cycles. The automatic sync/ID word detection feature is enabled by selecting Demodulator Mode 2 or 3 in the demodulator set-up register. Do this by setting R4_DB (25:23) = [010] or [011]. Bits R5_DB (4:5) are used to set the length of the sync/ID word, which can be 12, 16, 20, or 24 bits long. The transmitter must transmit the MSB of the sync byte first and the LSB last to ensure proper alignment in the receiver sync byte detection hardware. For systems using FEC, an error tolerance parameter can also be programmed that accepts a valid match when up to three bits of the word are incorrect. The error tolerance value is assigned in R5_DB (6:7).
AUTOMATIC SYNC WORD RECOGNITION
The ADF7020-1 also supports automatic detection of the sync or ID fields. To activate this mode, the sync (or ID) word must be preprogrammed in the ADF7020-1. In receive mode, this
Table 11. Sensitivity Values for Varying RF Frequency and Data Rates
Deviation in FSK Mode 10 kHz 5 kHz 10 kHz 5 kHz 10 kHz 5 kHz FSK Sensitivity at BER = 1E-3, Correlator Demodulator -113.2 dBm -119.5 dBm -114.2 dBm -120 dBm -113.2 dBm -119.8 dBm FSK Sensitivity at BER = 1E-3, Linear Demodulator -106.2 dBm -109.2 dBm -108.0 dBm -110.1 dBm -107.0 dBm -109.0 dBm ASK Sensitivity at BER = 1E-3 -110.8 -116.8 dBm -111.8 dBm -118 dBm -110.5 dBm -116.8 dBm
Frequency 135 MHz 135 MHz 315 MHz 315 MHz 610 MHz 610 MHz
Data Rate (NRZ) 9.6 kbps 1.0 kbps 9.6 kbps 1.0 kbps 9.6 kbps 1.0 kbps
Rev. 0 | Page 24 of 48
ADF7020-1 APPLICATIONS
LNA/PA MATCHING
The ADF7020-1 exhibits optimum performance in terms of sensitivity, transmit power, and current consumption only if its RF input and output ports are properly matched to the antenna impedance. For cost-sensitive applications, the ADF7020-1 is equipped with an internal Rx/Tx switch, which facilitates the use of a simple combined passive PA/LNA matching network. Alternatively, an external Rx/Tx switch, such as the Analog Devices ADG919, can be used, which yields a slightly improved receiver sensitivity and lower transmitter power consumption. in a back-to-back configuration. Due to the asymmetry of the network with respect to ground, a compromise between the input reflection coefficient and the maximum differential signal swing at the LNA input must be established. The use of appropriate CAD software is strongly recommended for this optimization. Depending on the antenna configuration, the user might need a harmonic filter at the PA output to satisfy the spurious emission requirement of the applicable government regulations. The harmonic filter can be implemented in various ways, such as a discrete LC pi or T-stage filter. The immunity of the ADF7020-1 to strong out-of-band interference can be improved by adding a band-pass filter in the Rx path, or alternatively by selecting one of the high linearity modes outlined in Table 6.
External Rx/Tx Switch
Figure 33 shows a configuration using an external Rx/Tx switch. This configuration allows an independent optimization of the matching and filter network in the transmit and receive path and is therefore more flexible and less difficult to design than the configuration using the internal Rx/Tx switch. The PA is biased through Inductor L1, and C1 blocks the dc current. Both elements, L1 and C1, also form the matching network, which transforms the source impedance into the optimum PA load impedance, ZOPT_PA.
VBAT L1 OPTIONAL LPF ANTENNA ZOPT_PA ZIN_RFIN OPTIONAL BPF (SAW) CA LA RFIN LNA RFINB PA_OUT PA
Internal Rx/Tx Switch
Figure 34 shows the ADF7020-1 in a configuration where the internal Rx/Tx switch is used with a combined LNA/PA matching network. This is the configuration used in the ADF7020-1DBX Evaluation boards. For most applications, the slight performance degradation of 1 dB to 2 dB caused by the internal Rx/Tx switch is acceptable, allowing the user to take advantage of the cost saving potential of this solution. The design of the combined matching network must compensate for the reactance presented by the networks in the Tx and the Rx paths, taking the state of the Rx/Tx switch into consideration.
VBAT L1 PA_OUT PA ANTENNA OPTIONAL BPF OR LPF CA ZOPT_PA ZIN_RFIN RFIN LA LNA RFINB
C1
ADG919
Rx/Tx - SELECT CB
ADF7020-1
Figure 33. ADF7020-1 with External Rx/Tx Switch
05669-033
ZIN_RFIN
ZOPT_PA depends on various factors, such as the required output power, the frequency range, the supply voltage range, and the temperature range. Selecting an appropriate ZOPT_PA helps to minimize the Tx current consumption in the application. The Specifications section lists a number of ZOPT_PA values for representative conditions. Under certain conditions, however, it is recommended to obtain a suitable ZOPT_PA value by means of a load-pull measurement. Due to the differential LNA input, the LNA matching network must be designed to provide both a single-ended to differential conversion and a complex conjugate impedance match. The network with the lowest component count that can satisfy these requirements is the configuration shown in Figure 33, which consists of two capacitors and one inductor. A first-order implementation of the matching network can be obtained by understanding the arrangement as two L type matching networks
CB
ADF7020-1
Figure 34. ADF7020-1 with Internal Rx/Tx Switch
The procedure typically requires several iterations until an acceptable compromise is reached. The successful implementation of a combined LNA/PA matching network for the ADF7020-1 is critically dependent on the availability of an accurate electrical model for the PC board. In this context, the use of a suitable CAD package is strongly recommended. To avoid this effort, however, a small form-factor reference design for the ADF7020-1 is provided, including matching and harmonic filter components. The design is on a 2-layer PCB to minimize cost. Gerber files are available on the www.analog.com website.
Rev. 0 | Page 25 of 48
05669-034
ZIN_RFIN
ADF7020-1
TRANSMIT PROTOCOL AND CODING CONSIDERATIONS
PREAMBLE DATA FIELD CRC
05669-035
INTERFACING TO MICROCONTROLLER/DSP
Low level device drivers are available for interfacing to the ADF7020-1, the ADI ADuC84x microcontroller parts, or the Blackfin ADSP-BF53x DSPs using the hardware connections shown in Figure 36 and Figure 37.
ADuC84x MISO MOSI SCLOCK SS P3.7 P3.2/INT0 P2.4 GPIO P2.5 P2.6 P2.7 CE INT/LOCK SREAD SLE SDATA SCLK
05669-036 05669-037
SYNC WORD
ID FIELD
Figure 35. Typical Format of a Transmit Protocol
A dc-free preamble pattern is recommended for FSK/ASK/ OOK demodulation. The recommended preamble pattern is a dc-free pattern such as a 10101010 ... pattern. Preamble patterns with longer run-length constraints, such as 11001100..., can also be used. However, this results in a longer synchronization time of the received bit stream in the receiver. Manchester coding can be used for the entire transmit protocol. However, the remaining fields that follow the preamble header do not have to use dc-free coding. For these fields, the ADF7020-1 can accommodate coding schemes with a runlength of up to 6 bits without any performance degradation. If longer run-length coding must be supported, the ADF7020-1 has several other features that can be activated. These involve a range of programmable options that allow the envelope detector output to be frozen after preamble acquisition.
ADF7020-1
TxRxDATA RxCLK
Figure 36.ADuC84x to ADF7020-1 Connection Diagram
ADSP-BF533 SCK MOSI MISO PF5 RSCLK1 DT1PRI DR1PRI RFS1 PF6 VCC GND INT/LOCK CE VCC GND
ADF7020-1
SCLK SDATA SREAD SLE TxRxCLK TxRxDATA
DEVICE PROGRAMMING AFTER INITIAL POWER-UP
Table 12 lists the minimum number of writes needed to set up the ADF7020-1 in either Tx or Rx mode after CE is brought high. Additional registers can also be written to tailor the part to a particular application, such as setting up sync byte detection or enabling AFC. When going from Tx to Rx or vice versa, the user needs to write only to the N register to alter the LO by 200 kHz and to toggle the Tx/Rx bit.
Table 12. Minimum Register Writes Required for Tx/Rx Setup
Mode Tx Rx (OOK) Rx (G/FSK) Tx <-> Rx Reg 0 Reg 0 Reg 0 Reg 0 Reg 1 Reg 1 Reg 1 Registers Reg 2 Reg 2 Reg 2
Figure 37.ADSP-BF533 to ADF7020-1 Connection Diagram
Reg 4 Reg 4
Reg 6 Reg 6
Figure 38 and Figure 39 show the recommended programming sequence and associated timing for power-up from standby mode.
Rev. 0 | Page 26 of 48
ADF7020-1
ADF7020-1 IDD
17.6mA TO 20.1mA 14mA
_XTAL
T0
3.65mA
2.0mA
AFC
T10
REG. READY WR3 WR4 WR6 WR0 WR1
VCO
T1
T2
T3
T4
T5 T6
T7 TON
AGC/ RSSI
CDR
T8
T9
RxDATA
TIME
05669-038
T11
TOFF
Figure 38. Rx Programming Sequence and Timing Diagram
Table 13. Power-Up Sequence Description
Parameter T0 T1 T2, T3, T5, T6, T7 T4 Value 2 ms 10 s 32 x 1/SPI_CLK 1 ms Description/Notes Crystal starts power-up after CE is brought high. This typically depends on the crystal type and the load capacitance specified. Time for regulator to power up. The serial interface can be written to after this time. Time to write to a single register. Maximum SPI_CLK is 25 MHz. The VCO can power-up in parallel with the crystal. This depends on the CVCO capacitance value used. A value of 22 nF is recommended as a trade-off between phase noise performance and power-up time. This depends on the number of gain changes the AGC loop needs to cycle through and AGC settings programmed. This is described in more detail in the AGC Information and Timing section. This is the time for the clock and data recovery circuit to settle. This typically requires 5-bit transitions to acquire sync and is usually covered by the preamble. This is the time for the automatic frequency control circuit to settle. This typically requires 16-bit transitions to acquire lock and is usually covered by an appropriate length preamble. Number of bits in payload by the bit period. Signal to Monitor CLKOUT pin MUXOUT pin
CVCO pin
T8
150 s
Analog RSSI on TEST_A pin (available by writing 0x3800 000C)
T9
5 x Bit_Period
T10
16 x Bit_Period
T11
Packet Length
Rev. 0 | Page 27 of 48
ADF7020-1
ADF7020-1 IDD
15mA TO 30mA
14mA
3.65mA
2.0mA
REG. READY
WR0 WR1
WR2
TON
TOFF
Figure 39. Tx Programming Sequence and Timing Diagram
Rev. 0 | Page 28 of 48
05669-039
T1
T2
T3
XTAL + VCO
T4
T5
TxDATA
TIME
T12
ADF7020-1 SERIAL INTERFACE
The serial interface allows the user to program the eleven 32-bit registers using a 3-wire interface (SCLK, SDATA, and SLE). It consists of a voltage level shifter, a 32-bit shift register, and 11 latches. Signals should be CMOS compatible. The serial interface is powered by the regulator and therefore is inactive when CE is low. Data is clocked into the register MSB first on the rising edge of each clock (SCLK). Data is transferred to one of the 11 latches on the rising edge of SLE. The destination latch is determined by the value of the four control bits (C4 to C1). These are the bottom 4 LSB, DB3 to DB0, as shown in the timing diagram in Figure 2. Data can also be read back on the SREAD pin.
RSSI Readback
The RSSI readback operation yields valid results in Rx mode with ASK or FSK signals. The format of the readback word is shown in Figure 40. It is comprised of the RSSI level information (Bits RV1 to RV7), the current filter gain (FG1, FG2), and the current LNA gain (LG1, LG2) setting. The filter and LNA gain are coded in accordance with the definitions in Register 9. With the reception of ASK modulated signals, averaging of the measured RSSI values improves accuracy. The input power can be calculated from the RSSI readback value as outlined in the RSSI/AGC.
Battery Voltage ADCIN/Temperature Sensor Readback
The battery voltage is measured at Pin VDD4. The readback information is contained in Bits RV1 to RV7. This also applies for the readback of the voltage at the ADCIN pin and the temperature sensor. From the readback information, the battery or ADCIN voltage can be determined using VBATTERY = (Battery_Voltage_Readback)/21.1 VADCIN = (ADCIN_Voltage_Readback)/42.1
READBACK FORMAT
The readback operation is initiated by writing a valid control word to the readback register and setting the readback-enable bit (R7_DB8 = 1). The readback can begin after the control word has been latched with the SLE signal. SLE must be kept high while the data is read out. Each active edge at the SCLK pin clocks the readback word out successively at the SREAD pin, as shown in Figure 3, starting with the MSB first. The data appearing at the first clock cycle following the latch operation must be ignored.
Silicon Revision Readback
The silicon revision readback word is valid without setting any other registers, especially directly after power-up. The silicon revision word is coded with four quartets in BCD format. The product code (PC) is coded with three quartets extending from Bits RV5 to RV16. The revision code (RV) is coded with one quartet extending from Bits RV1 to RV4. The product code for the ADF7020-1 should read back as PC = 0x200. The current revision code should read back as RC = 0x6.
AFC Readback
The AFC readback is valid only during the reception of FSK signals with either the linear or correlator demodulator active. The AFC readback value is formatted as a signed 16-bit integer comprised of Bits RV1 to RV16 and is scaled according to the following formula: FREQ_RB [Hz] = (AFC_READBACK x DEMOD_CLK)/215 In the absence of frequency errors, the FREQ_RB value is equal to the IF frequency of 200 kHz. Note that the down-converted input signal must not fall outside the bandwidth of the analogue IF filter for the AFC readback to yield a valid result. At lowinput signal levels, the variation in the readback value can be improved by averaging.
Filter Calibration Readback
The filter calibration readback word is contained in Bits RV1 to RV8 and is for diagnostic purposes only. Using the automatic filter calibration function, accessible through Register 6, is recommended. Before filter calibration is initiated Decimal 32 should be read back.
READBACK MODE DB15 AFC READBACK RSSI READBACK BATTERY VOLTAGE/ADCIN/ TEMP. SENSOR READBACK SILICON REVISION FILTER CAL READBACK RV16 X DB14 RV15 X DB13 RV14 X DB12 RV13 X DB11 RV12 X DB10 RV11 LG2
READBACK VALUE DB9 RV10 LG1 DB8 RV9 FG2 DB7 RV8 FG1 DB6 RV7 RV7 DB5 RV6 RV6 DB4 RV5 RV5 DB3 RV4 RV4 DB2 RV3 RV3 DB1 RV2 RV2 DB0 RV1 RV1
X RV16 0
X RV15 0
X RV14 0
X RV13 0
X RV12 0
X RV11 0
X RV10 0
X RV9 0
X RV8 RV8
RV7 RV7 RV7
RV6 RV6 RV6
RV5 RV5 RV5
RV4 RV4 RV4
RV3 RV3 RV3
RV2 RV2 RV2
RV1
05669-040
RV1 RV1
Figure 40. Readback Value Table
Rev. 0 | Page 29 of 48
ADF7020-1
REGISTER 0--N REGISTER
PLL ENABLE Tx/Rx
MUXOUT
8-BIT INTEGER-N
15-BIT FRACTIONAL-N
ADDRESS BITS
DB31
DB30
DB29
PLE1 DB28
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
C4 (0) DB3
C3 (0) DB2
C2 (0) DB1
TR1 0 1
TRANSMIT/ RECEIVE TRANSMIT RECEIVE
M15 0 0 0 . . . 1 1 1 1
M14 0 0 0 . . . 1 1 1 1
M13 0 0 0 . . . 1 1 1 1
... ... ... ... ... ... ... ... ... ... ...
M3 0 0 0 . . . 1 1 1 1
M2 0 0 1 . . . 0 0 1 1
M1 0 1 0 . . . 0 1 0 1
FRACTIONAL DIVIDE RATIO 0 1 2 . . . 32764 32765 32766 32767
PLE1 PLL ENABLE 0 1 M3 0 0 0 0 1 1 1 1 M2 0 0 1 1 0 0 1 1 M1 0 1 0 1 0 1 0 1 PLL OFF PLL ON MUXOUT REGULATOR READY (DEFAULT) R DIVIDER OUTPUT N DIVIDER OUTPUT DIGITAL LOCK DETECT ANALOG LOCK DETECT THREE-STATE PLL TEST MODES - TEST MODES
N8 0 0 . . . 1 1 1
N7 0 0 . . . 1 1 1
N6 0 1 . . . 1 1 1
N5 1 0 . . . 1 1 1
N4 1 0 . . . 1 1 1
N3 1 0 . . . 1 1 1
N2 1 0 . . . 0 1 1
N1 1 0 . . . 1 0 1
N COUNTER DIVIDE RATIO 31 32 . . . 253 254 255
C1 (0) DB0
05669-041
M15
M14
M13
M12
M11
M10
TR1
M3
M2
M1
M9
M8
M7
M6
M5
M4
M3
M2
Figure 41.
Notes
1. 2.
The Tx/Rx bit (R0_DB27) configures the part in Tx or Rx mode and also controls the state of the internal Tx/Rx switch.
FOUT = XTAL Fractional -N x ( Integer-N + ). R 215
Rev. 0 | Page 30 of 48
M1
N8
N7
N6
N5
N4
N3
N2
N1
ADF7020-1
REGISTER 1--OSCILLATOR/FILTER REGISTER
IF FILTER BW VCO BAND CP CURRENT
VCO BIAS
CLOCKOUT DIVIDE
XTAL DOUBLER
VCO ADJUST
XOSC ENABLE
R COUNTER
ADDRESS BITS
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
C4 (0) DB3
C3 (0) DB2
C2 (0) DB1
VA2 0 0 1 1
VA1 0 1 0 1
FREQUENCY OF OPERATION 850-920 860-930 870-940 880-950 V1 VCO BIAS CURRENT 0.375mA 0.625mA 3.875mA 0 1
X1 XTAL OSC 0 OFF 1 ON
VCO DIV-BY-2 DIRECT OUTPUT DIVIDE-BY-2 OUTPUT D1 0 1
R3 0 0 . . . 1
R2 0 1 . . . 1
R1 1 0 . . . 1
RF R COUNTER DIVIDE RATIO 1 2 . . . 7
VB4 0 0 . 1
VB3 0 0 . 1
VB2 0 1 . 1
VB1 1 0 . 1
XTAL DOUBLER DISABLE ENABLED
IR2 IR1 0 0 1 1 0 1 0 1
FILTER BANDWIDTH 100kHz 150kHz 200kHz NOT USED
Figure 42.
Notes
1. 2. 3.
Set the VCO adjust bits R1_DB (20:21) to 0 for normal operation. See Table 5 for the recommended VCO bias settings. The divide-by-2 block is enabled by setting R1_DB13. As this divide block is outside the PLL loop, users must program an N-value that corresponds to twice the divide-by-2 output frequency. The deviation frequency is also halved when divide-by-2 is enabled.
Rev. 0 | Page 31 of 48
05669-042
CP2 0 0 1 1
CP1 RSET 0 1 0 1
ICP(MA) 3.6k 0.3 0.9 1.5 2.1
CL4 0 0 0 . . . 1
CL3 0 0 0 . . . 1
CL2 0 0 1 . . . 1
CL1 0 1 0 . . . 1
CLKOUT DIVIDE RATIO OFF 2 4 . . . 30
C1 (1) DB0
DD2
DD1
VA2
VA1
VB4
VB3
VB2
VB1
CL4
CL3
CL2
CL1
IR2
IR1
D1
R3
R2
R1
V1
X1
ADF7020-1
REGISTER 2--TRANSMIT MODULATION REGISTER (ASK/OOK MODE)
MUTE PA UNTIL LOCK PA ENABLE INDEX COUNTER TxDATA INVERT
PA BIAS GFSK MOD CONTROL MODULATION PARAMETER POWER AMPLIFIER MODULATION SCHEME ADDRESS BITS
DB31
DB30
DB29
DB28
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
C4 (0) DB3
C3 (0) DB2
C2 (1) DB1
PE1 IC2 IC1 MC3 MC2 MC1 X X X X X 0 1
POWER AMPLIFIER OFF ON
DI1 0 1 TxDATA TxDATA
MUTE PA UNTIL MP1 LOCK DETECT HIGH 0 1 OFF ON
PA2 0 0 1 1
PA1 0 1 0 1
PA BIAS 5A 7A 9A 11A
S3 0 0 0 0 1
S2 0 0 1 1 1
S1 0 1 0 1 1
MODULATION SCHEME FSK GFSK ASK OOK GOOK
POWER AMPLIFIER OUTPUT LOW LEVEL D1 D2 D5 . D6 X 0 0 0 0 . . 1 X X 0 0 . . . 1 . . . . . . . . X X 0 0 1 . . 1 X X 0 1 0 . . 1 OOK MODE PA OFF -16.0dBm -16 + 0.45dBm -16 + 0.90dBm . . 13dBm
POWER AMPLIFIER OUTPUT HIGH LEVEL P1 P2 . . P6 0 0 0 0 . . 1 . . . . . . 1 . . . . . . . X 0 0 1 . . 1 X 0 1 0 . . 1 PA OFF -16.0dBm -16 + 0.45dBm -16 + 0.90dBm . . 13dBm
C1 (0) DB0
05669-043
MC3
MC2
MC1
MP1
PA2
PA1
Figure 43.
Notes
1. 2. 3.
Figure 13 shows how the PA bias affects the power amplifier level. The default level is 9 A. If you need maximum power, program this value to 11 A. In ASK/OOK, Manchester encoding is recommended to keep the data run length limit to 2 bits. See the ASK/OOK Operation section for more details on dealing with longer run lengths. D7, D8, and D9 are don't care bits.
Rev. 0 | Page 32 of 48
PE1
DI1
IC2
IC1
D9
D8
D7
D6
D5
D4
D3
D2
D1
P6
P5
P4
P3
P2
P1
S3
S2
S1
ADF7020-1
REGISTER 2--TRANSMIT MODULATION REGISTER (FSK MODE)
PA BIAS GFSK MOD CONTROL MODULATION PARAMETER POWER AMPLIFIER MODULATION SCHEME
MUTE PA UNTIL LOCK PA ENABLE INDEX COUNTER TxDATA INVERT
ADDRESS BITS
DB31
DB30
DB29
DB28
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
C4 (0) DB3
C3 (0) DB2
C2 (1) DB1
PE1 IC2 IC1 MC3 MC2 MC1 X X X X X 0 1
POWER AMPLIFIER OFF ON
DI1 0 1 TxDATA TxDATA
FOR FSK MODE, D9 D3 .... D2 0 0 0 0 . 1 .... .... .... .... .... .... 0 0 0 0 . 1 0 0 1 1 . 1
MUTE PA UNTIL MP1 LOCK DETECT HIGH D1 0 1 0 1 . 1 F DEVIATION PLL MODE 1 x FSTEP 2 x FSTEP 3 x FSTEP . 511 x FSTEP 0 1 OFF ON
PA2 0 0 1 1
PA1 0 1 0 1
PA BIAS 5A 7A 9A 11A
S3 0 0 0 0 1
S2 0 0 1 1 1
S1 0 1 0 1 1
MODULATION SCHEME FSK GFSK ASK OOK GOOK
POWER AMPLIFIER OUTPUT LEVEL P6 . . P2 P1 0 0 0 0 . . 1 . . . . . . 1 . . . . . . . X 0 0 1 . . 1 X 0 1 0 . . 1 PA OFF -16.0dBm -16 + 0.45dBm -16 + 0.90dBm . . 13dBm
C1 (0) DB0
05669-044
MC3
MC2
MC1
MP1
PA2
PA1
Figure 44.
Notes
1. 2.
FSTEP = PFD/214. PA bias default = 9 A.
Rev. 0 | Page 33 of 48
PE1
DI1
IC2
IC1
D9
D8
D7
D6
D5
D4
D3
D2
D1
P6
P5
P4
P3
P2
P1
S3
S2
S1
ADF7020-1
REGISTER 2--TRANSMIT MODULATION REGISTER (GFSK/GOOK MODE)
MUTE PA UNTIL LOCK PA ENABLE INDEX COUNTER TxDATA INVERT
PA BIAS GFSK MOD CONTROL MODULATION PARAMETER POWER AMPLIFIER MODULATION SCHEME ADDRESS BITS
DB31
DB30
DB29
DB28
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
C4 (0) DB3
C3 (0) DB2
C2 (1) DB1
D7 0 0 0 0 . 1 TxDATA TxDATA
... ... ... ... ... ... ...
D3 0 0 0 0 . 1
D2 0 0 1 1 . 1
D1 0 1 0 1 . 1
DIVIDER_FACTOR INVALID 1 2 3 . 127
PE1 0 1
POWER AMPLIFIER OFF ON
DI1 0 1
MUTE PA UNTIL MP1 LOCK DETECT HIGH 0 1 OFF ON
PA2 0 0 1 1
PA1 0 1 0 1
PA BIAS 5A 7A 9A 11A D9 0 0 1 1 INDEX_COUNTER 16 32 64 128 D8 0 1 0 1
GAUSSIAN - OOK MODE NORMAL MODE OUTPUT BUFFER ON BLEED CURRENT ON BLEED/BUFFER ON
S3 0 0 0 0 1
S2 0 0 1 1 1
S1 0 1 0 1 1
MODULATION SCHEME FSK GFSK ASK OOK GOOK
IC2 0 0 1 1
IC1 0 1 0 1
POWER AMPLIFIER OUTPUT LEVEL P1 P2 . . P6 0 0 0 0 . . 1 . . . . . . 1 . . . . . . . X 0 0 1 . . 1 X 0 1 0 . . 1 PA OFF -16.0dBm -16 + 0.45dBm -16 + 0.90dBm . . 13dBm
05669-045
MC3 MC2 MC1 GFSK_MOD_CONTROL 0 0 . 1 0 0 . 1 0 1 . 1 0 1 . 7
Figure 45.
Notes
1. 2. 3.
GFSK_DEVIATION = (2GFSK_MOD_CONTROL x PFD)/212. Data rate = PFD/(INDEX_COUNTER x DIVIDER_FACTOR). PA bias default = 9 A.
Rev. 0 | Page 34 of 48
C1 (0) DB0
MC3
MC2
MC1
MP1
PA2
PA1
PE1
DI1
IC2
IC1
D9
D8
D7
D6
D5
D4
D3
D2
D1
P6
P5
P4
P3
P2
P1
S3
S2
S1
ADF7020-1
REGISTER 3--RECEIVER CLOCK REGISTER
DEMOD CLOCK DIVIDE BB OFFSET CLOCK DIVIDE
ADDRESS BITS
SEQUENCER CLOCK DIVIDE
CDR CLOCK DIVIDE
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1 C2(1)
C4(0)
C3(0)
SK8 0 0 . 1 1
SK7 0 0 . 1 1
... ... ... ... ... ...
SK3 0 0 . 1 1
SK2 0 1 . 1 1
SK1 1 0 . 0 1
SEQ_CLK_DIVIDE 1 2 . 254 255 OK2 0 0 1 1
BK2 0 0 1 OK1 0 1 0 1
BK1 0 1 x
BBOS_CLK_DIVIDE 4 8 16
DEMOD_CLK_DIVIDE 4 1 2 3
FS8 0 0 . 1 1
FS7 0 0 . 1 1
... ... ... ... ... ...
FS3 0 0 . 1 1
FS2 0 1 . 1 1
FS1 1 0 . 0 1
CDR_CLK_DIVIDE 1 2 . 254 255
C1(1)
05669-046
OK2
OK1
BK2
Figure 46.
Notes
1.
Baseband offset clock frequency (BBOS_CLK) must be greater than 1 MHz and less than 2 MHz, where
BBOS _ CLK = XTAL . BBOS _ CLK _ DIVIDE
2.
The demodulator clock (DEMOD_CLK) must be <12 MHz for FSK and <6 MHz for ASK, where
DEMOD _ CLK = XTAL . DEMOD _ CLK _ DIVIDE
3.
Data/clock recovery frequency (CDR_CLK) should be within 2% of (32 x data rate), where
CDR _ CLK = DEMOD _ CLK . CDR _ CLK _ DIVIDE
Note that this might affect your choice of XTAL, depending on the desired data rate. 4. The sequencer clock (SEQ_CLK) supplies the clock to the digital receive block. It should be close to 100 kHz for FSK and close to 40 kHz for ASK:
SEQ _ CLK = XTAL . SEQ _ CLK _ DIVIDE
Rev. 0 | Page 35 of 48
BK1
SK8
SK7
SK6
SK5
SK4
SK3
SK2
SK1
FS8
FS7
FS6
FS5
FS4
FS3
FS2
FS1
DB0
ADF7020-1
REGISTER 4--DEMODULATOR SET-UP REGISTER
DEMOD LOCK/ DB24 SYNC WORD MATCH DEMOD SELECT
DEMODULATOR LOCK SETTING
POSTDEMODULATOR BW
ADDRESS BITS
DB31
DB30
DB29
DB28
DB27
DB26
DB25
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DW10 DB15
DW9 DB14
DW8 DB13
DW7 DB12
DW6 DB11
DW5 DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1 C2(0)
C4(0)
C3(1)
DS2 0 0 1 1 DEMOD MODE LM2 LM1 DL8 0 1 2 3 4 5 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 X DL8 DEMOD LOCK/SYNC WORD MATCH SERIAL PORT CONTROL--FREE RUNNING SERIAL PORT CONTROL--LOCK THRESHOLD SYNC WORD DETECT--FREE RUNNING SYNC WORD DETECT--LOCK THRESHOLD INTERRUPT/LOCK PIN LOCKS THRESHOLD DEMOD LOCKED AFTER DL8-DL1 BITS INT/LOCK PIN - - OUTPUT OUTPUT INPUT -
DS1 0 1 0 1
DEMODULATOR TYPE LINEAR DEMODULATOR CORRELATOR/DEMODULATOR ASK/OOK INVALID
MODE5 ONLY DL8 0 0 0 . 1 1 DL7 0 0 0 . 1 1 ... ... ... ... ... ... ... DL3 0 0 0 . 1 1 DL2 0 0 1 . 1 1 DL1 0 1 0 . 0 1 LOCK_THRESHOLD_TIMEOUT 0 1 2 . 254 255
C1(0)
05669-047
DW4
DW3
DW2
DW1
LM2
LM1
DS2
Figure 47.
Notes
1. 2. 3.
Demodulator Modes 1, 3, 4, and 5 are modes that can be activated to allow the ADF7020-1 to demodulate data-encoding schemes that have run-length constraints greater than 7. Post_Demod_BW = 211 FCUTOFF/DEMOD_CLK, where the cutoff frequency (FCUTOFF) of the postdemodulator filter should typically be 0.75 times the data rate. For Mode 5, the timeout delay to lock threshold = (LOCK_THRESHOLD_SETTING)/SEQ_CLK, where SEQ_CLK is defined in the Register 3--Receiver Clock Register section.
Rev. 0 | Page 36 of 48
DS1
DL8
DL7
DL6
DL5
DL4
DL3
DL2
DL1
DB0
ADF7020-1
REGISTER 5--SYNC BYTE REGISTER
MATCHING TOLERANCE SYNC BYTE LENGTH
SYNC BYTE SEQUENCE CONTROL BITS
DB31
DB30
DB29
DB28
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1 C2(0)
C4(0)
C3(1)
PL2 0 0 1 1
PL1 0 1 0 1
SYNC BYTE LENGTH 12 BITS 16 BITS 20 BITS 24 BITS
MATCHING MT2 MT1 TOLERANCE
05669-048
0 0 1 1
0 1 0 1
0 ERRORS 1 ERROR 2 ERRORS 3 ERRORS
Figure 48.
Notes
1. 2. 3. 4.
Sync byte detect is enabled by programming Bits R4_DB (25:23) to [010] or [011]. This register allows a 24-bit sync byte sequence to be stored internally. If the sync byte detect mode is selected, the INT/LOCK pin goes high when the sync byte is detected in Rx mode. Once the sync word detect signal goes high, it goes low again after nine data bits. The transmitter must transmit the MSB of the sync byte first and the LSB last to ensure proper alignment in the receiver sync byte detection hardware. Choose a sync byte pattern that has good autocorrelation properties, for example, an unequal amount of digital 1s and 0s.
Rev. 0 | Page 37 of 48
C1(1)
MT2
MT1
PL2
PL1
DB0
ADF7020-1
REGISTER 6--CORRELATOR/DEMODULATOR REGISTER
LNA MODE IF FILTER CAL MIXER LINEARITY DOT PRODUCT
Rx RESET
LNA CURRENT
RxDATA INVERT
IF FILTER DIVIDER
DISCRIMINATOR BW
ADDRESS BITS
DB31
DB30
DB29
DB28
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
TD10 DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1 C2(1)
C4(0)
C3(1)
CA1 FILTER CAL DEMOD RESET CDR RESET RxDATA INVERT RxDATA RxDATA 0 1 NO CAL CALIBRATE
DP1 0 1 LG1 0 1 LI2 0 LI1 0 LNA BIAS 800A (DEFAULT)
DOT PRODUCT CROSS PRODUCT DOT PRODUCT LNA MODE DEFAULT REDUCED GAIN
ML1 MIXER LINEARITY 0 1 DEFAULT HIGH
RI1 0 1
FC9 0 0 . . . . 1
. . . . . . . .
FC6 0 0 . . . . 1
FC5 0 0 . . . . 1
FC4 0 0 . . . . 1
FC3 0 0 . . . . 1
FC2 0 1 . . . . 1
FC1 1 0 . . . . 1
FILTER CLOCK DIVIDE RATIO 1 2 . . . . 511
Figure 49.
Notes
1. 2. 3. 4. 5. 6.
See the FSK Correlator/Demodulator section for an example of how to determine register settings. Nonadherence to correlator programming guidelines results in poorer sensitivity. The filter clock is used to calibrate the IF filter. The filter clock divide ratio should be adjusted so that the frequency is 50 kHz. The formula is XTAL/FILTER_CLOCK_DIVIDE. The filter should be calibrated only when the crystal oscillator is settled. The filter calibration is initiated every time Bit R6_DB19 is set high. Discriminator_BW = (DEMOD_CLK x K)/(800 x 103). See the FSK Correlator/Demodulator section. Maximum value = 600. When LNA Mode = 1 (reduced gain mode), this prevents the Rx from selecting the highest LNA gain setting. This might be used when linearity is a concern. See Table 6 for details of the Rx modes.
Rev. 0 | Page 38 of 48
05669-049
C1(0)
ML1
CA1
LG1
DP1
FC9
FC8
FC7
FC6
FC5
FC4
FC3
FC2
FC1
TD9
TD8
TD7
TD6
TD5
TD4
TD3
TD2
TD1
RI1
LI2
LI1
DB0
ADF7020-1
REGISTER 7--READBACK SET-UP REGISTER
READBACK SELECT DB8 RB3 DB7 RB2 DB6 RB1
ADC MODE DB5 AD2 DB4 AD1 DB3 C4(0)
CONTROL BITS DB2 C3(1) DB1 C2(1) DB0 C1(1)
RB3 READBACK 0 1 DISABLED ENABLED RB2 RB1 READBACK MODE 0 0 1 1 0 1 0 1 AFC WORD ADC OUTPUT FILTER CAL SILICON REV
AD2 AD1 ADC MODE 0 0 1 1 0 1 0 1 MEASURE RSSI BATTERY VOLTAGE TEMP SENSOR TO EXTERNAL PIN
Figure 50.
Notes
1.
Readback of the measured RSSI value is valid only in Rx mode. To enable readback of the battery voltage, the temperature sensor, or the voltage at the external pin in Rx mode, users must disable the AGC function in Register 9. To read back these parameters in Tx mode, users must first power up the ADC using Register 8, because it is off by default in Tx mode to save power. This is the recommended method of using the battery readback function since most configurations typically require use of the AGC function. Readback of the AFC word is valid in Rx mode only if either the linear demodulator or the correlator/demodulator is active. See the Readback Format section for more information.
2. 3.
Rev. 0 | Page 39 of 48
05669-050
ADF7020-1
REGISTER 8--POWER-DOWN TEST REGISTER
INTERNAL Tx/Rx SWITCH ENABLE PA ENABLE Rx MODE LNA/MIXER ENABLE DEMOD ENABLE ADC ENABLE FILTER ENABLE VCO ENABLE
LOG AMP/ RSSI
SYNTH ENABLE
CONTROL BITS
DB15
DB14
DB13 PD7
DB12 SW1
DB11 LR2
DB10 LR1
DB9 PD6
DB8 PD5
DB7 PD4
DB6 PD3
DB5 PD2
DB4 PD1
DB3 C4(1)
DB2 C3(0)
DB1 C2(0)
DB0 C1(0)
PD7 0 1
PA (Rx MODE) PA OFF PA ON SW1 Tx/Rx SWITCH 0 1 DEFAULT (ON) OFF LR2 X X LR1 0 1 RSSI MODE RSSI OFF RSSI ON PD6 0 1 DEMOD ENABLE DEMOD OFF DEMOD ON PD5 0 1 PD4 0 1 ADC ENABLE ADC OFF ADC ON PD3 0 1
PLE1 (FROM REG 0) 0 0 0 0 1
PD2 0 0 1 1 X
PD1 0 1 0 1 X
LOOP CONDITION VCO/PLL OFF PLL ON VCO ON PLL/VCO ON PLL/VCO ON
LNA/MIXER ENABLE LNA/MIXER OFF LNA/MIXER ON
FILTER ENABLE FILTER OFF FILTER ON
Figure 51.
Notes
1. 2.
For a combined LNA/PA matching network, Bit R8_DB12 should always be set to 0. This is the power-up default condition. It is not necessary to write to this register under normal operating conditions.
Rev. 0 | Page 40 of 48
05669-051
ADF7020-1
REGISTER 9--AGC REGISTER
GAIN CONTROL AGC SEARCH FILTER CURRENT
DIGITAL TEST IQ
FILTER GAIN
LNA GAIN
AGC HIGH THRESHOLD
AGC LOW THRESHOLD
ADDRESS BITS
DB31
DB30
DB29
DB28
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1 C2(0)
C4(1)
C3(0)
FI1 0 1
FILTER CURRENT LOW HIGH FG2 0 0 1 1 FG1 0 1 0 1 FILTER GAIN 8 24 72 INVALID
GS1 AGC SEARCH 0 1 AUTO AGC HOLD SETTING GL7 0 0 0 0 . . . 1 1 1 GL6 0 0 0 0 . . . 1 1 1 GL5 0 0 0 0 . . . 1 1 1 GL4 0 0 0 0 . . . 1 1 1 GL3 0 0 0 1 . . . 1 1 1 GL2 0 1 1 0 . . . 0 1 1 GL1 1 0 1 0 . . . 1 0 1
AGC LOW THRESHOLD 1 2 3 4 . . . 61 62 63
GC1 GAIN CONTROL 0 1 AUTO USER
RSSI LEVEL GH7 GH6 GH5 GH4 GH3 GH2 GH1 CODE 0 0 0 0 . . . 1 1 1 0 0 0 0 . . . 0 0 0 0 0 0 0 . . . 0 0 1 0 0 0 0 . . . 1 1 0 0 0 0 1 . . . 1 1 0 0 1 1 0 . . . 1 1 0 1 0 1 0 . . . 0 1 0 1 2 3 4 . . . 78 79 80
LG2 0 0 1 1
LG1 0 1 0 1
LNA GAIN <1 3 10 30
C1(1)
05669-052
GC1
GH7
GH6
GH5
GH4
GH3
GH2
GH1
GS1
FG2
FG1
LG2
LG1
GL7
GL6
GL5
GL4
GL3
GL2
Figure 52.
Notes
1. 2. 3.
Default AGC_LOW_THRESHOLD = 30, default AGC_HIGH_THRESHOLD = 70. See the RSSI/AGC for details. AGC high and low settings must be more than 30 settings apart to ensure correct operation. LNA gain of 30 is available only if the LNA mode bit, R6_DB15, is set to 0.
Rev. 0 | Page 41 of 48
GL1
FI1
DB0
ADF7020-1
REGISTER 10--AGC 2 REGISTER
RESERVED
I/Q PHASE ADJUST
UP/DOWN
SELECT I/Q
SELECT I/Q
I/Q GAIN ADJUST
AGC DELAY
LEAK FACTOR
PEAK RESPONSE
ADDRESS BITS
DB31
DB30
DB29
SIQ2 DB28
DB27
DB26
DB25
DB24
DB23
SIQ1 DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
C4 (1) DB3
C3 (0) DB2
C2 (1) DB1
0 1
PHASE TO I CHANNEL PHASE TO Q CHANNEL
0 1
GAIN TO I CHANNEL GAIN TO Q CHANNEL
DEFAULT = 0xA
DEFAULT = 0x2
Figure 53.
Notes
1.
This register is not used under normal operating conditions.
REGISTER 11--AFC REGISTER
DB20 AFC ENABLE
AFC SCALING COEFFICIENT
CONTROL BITS
DB31
DB30
DB29
DB28
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
C4(0)
C3(0)
C2(1)
0 1
OFF ON
Figure 54.
Notes
1. 2.
See the Internal AFC section to program AFC scaling coefficient bits. The AFC scaling coefficient bits can be programmed using the following formula: AFC_Scaling_Coefficient = Round((500 x 224)/XTAL).
Rev. 0 | Page 42 of 48
05669-054
INTERNAL AE1 AFC
C1(0)
AE1
M16
M15
M14
M13
M12
M11
M10
M9
M8
M7
M6
M5
M4
M3
M2
M1
DB0
05669-053
SIQ2 SELECT IQ
SIQ2 SELECT IQ
DEFAULT = 0xA
C1 (0) DB0
GC5
GC4
GC3
GC2
GC1
UD1
DH4
DH3
DH2
DH1
GL7
GL6
GL5
GL4
PH4
PH3
PH2
PH1
PR4
PR3
PR2
PR1
R1
ADF7020-1
REGISTER 12--TEST REGISTER
DB31 PRESCALER OSC TEST COUNTER RESET SOURCE FORCE LD HIGH
ANALOG TEST MUX
IMAGE FILTER ADJUST
DIGITAL TEST MODES
- TEST MODES
PLL TEST MODES
ADDRESS BITS
DB30
DB29
DB28
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1 C2(0)
C4(1)
C3(1)
P 0 1
PRESCALER 4/5 (DEFAULT) 8/9 CS1 0 1 CAL SOURCE INTERNAL SERIAL IF BW CAL
DEFAULT = 32. INCREASE NUMBER TO INCREASE BW IF USER CAL ON
CR1 COUNTER RESET 0 1 DEFAULT RESET
C1(0)
05669-055
PRE
QT1
CS1
SF6
SF5
SF4
SF3
SF2
SF1
T9
T8
T7
T6
T5
T4
T3
T2
Figure 55.
Using the Test DAC on the ADF7020-1 to Implement Analog FM Demodulation and Measuring of SNR
The test DAC allows the output of the postdemodulator filter for both the linear and correlator/demodulators (Figure 31 and Figure 32) to be viewed externally. It takes the 16-bit filter output and converts it to a high frequency, single-bit output using a second-order error feedback - converter. The output can be viewed on the CLKOUT pin. This signal, when IF filtered appropriately, can then be used to * Monitor the signals at the FSK/ASK postdemodulator filter output. This allows the demodulator output SNR to be measured. Eye diagrams can also be constructed of the received bit stream to measure the received signal quality. Provide analog FM demodulation.
Programming the test register, Register 12, enables the test DAC. In correlator mode, this can be done by writing Digital Test Mode 7 or 0x0001C00C. To view the test DAC output when using the linear demodulator, the user must remove a fixed offset term from the signal using Register 13. This offset is nominally equal to the IF frequency. The user can determine the value to program by using the frequency error readback to determine the actual IF and then programming half this value into the offset removal field. It also has a signal gain term to allow the usage of the maximum dynamic range of the DAC.
Setting Up the Test DAC
* * Digital test modes = 7: enables the test DAC, with no offset removal (0x0001 C00C). Digital test modes = 10: enables the test DAC, with offset removal (needed for linear demod only, 0x02 800C).
*
While the correlators and filters are clocked by DEMOD_CLK, CDR_CLK clocks the test DAC. Note that, although the test DAC functions in a regular user mode, the best performance is achieved when the CDR_CLK is increased up to or above the frequency of DEMOD_CLK. The CDR block does not function when this condition exists.
The output of the active demodulator drives the DAC; that is, if the FSK correlator/demodulator is selected, the correlator filter output drives the DAC.
Rev. 0 | Page 43 of 48
T1
DB0
ADF7020-1
REGISTER 13--OFFSET REMOVAL AND SIGNAL GAIN REGISTER
TEST DAC GAIN TEST DAC OFFSET REMOVAL PULSE EXTENSION KI KP CONTROL BITS
DB31
DB30
DB29
DB28
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1 C2(0)
C4(1)
C3(1)
PE4 0 0 0 . . . 1
PE3 0 0 0 . . . 1
PE2 0 0 1 . . . 1
PE1 0 1 0 . . . 1
PULSE EXTENSION NORMAL PULSE WIDTH 2 x PULSE WIDTH 3 x PULSE WIDTH . . . 16 x PULSE WIDTH
C1(1)
05669-056
PE4
PE3
PE2
Figure 56.
Notes
1.
Because the linear demodulator's output is proportional to frequency, it usually consists of an offset combined with a relatively low signal. Up to a maximum of a 300 kHz offset can be removed and gained to use the full dynamic range of the DAC: DAC_input = (2Test_DAC_Gain) x (Signal - Test_DAC_Offset_Removal/4096).
Rev. 0 | Page 44 of 48
PE1
DB0
ADF7020-1 OUTLINE DIMENSIONS
7.00 BSC SQ 0.60 MAX 0.60 MAX
37 36
0.30 0.23 0.18
48 1
PIN 1 INDICATOR
PIN 1 INDICATOR
TOP VIEW
6.75 BSC SQ
EXPOSED PAD
(BOTTOM VIEW)
4.25 4.10 SQ 3.95
0.50 0.40 0.30
25 24
12 13
0.25 MIN 5.50 REF
1.00 0.85 0.80
12 MAX
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.50 BSC
SEATING PLANE
0.20 REF
COPLANARITY 0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
Figure 57. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 7 mm x 7 mm Body, Very Thin Quad (CP-48-3) Dimensions shown in millimeters
ORDERING GUIDE
Model ADF7020-1BCPZ 1 ADF7020-1BCPZ-RL1 ADF7020-1BCPZ-RL71 EVAL-ADF70XXMB EVAL-ADF70XXMB2 EVAL-ADF7020-1DB4 EVAL-ADF7020-1DB5
1
Temperature Range -40C to +85C -40C to +85C -40C to +85C
Package Description 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Control Mother Board Evaluation Platform 400 MHz to 435 MHz Daughter Board 135 MHz to 650 MHz Daughter Board
Package Option CP-48-3 CP-48-3 CP-48-3
Z = Pb-free part.
Rev. 0 | Page 45 of 48
ADF7020-1 NOTES
Rev. 0 | Page 46 of 48
ADF7020-1 NOTES
Rev. 0 | Page 47 of 48
ADF7020-1 NOTES
(c) 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05669-0-12/05(0)
Rev. 0 | Page 48 of 48

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